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Searched refs:R300_SCLK_CNTL2 (Results 1 – 2 of 2) sorted by relevance

/openbsd/sys/dev/pci/drm/radeon/
H A Dradeon_clocks.c631 tmp = RREG32_PLL(R300_SCLK_CNTL2); in radeon_legacy_set_clock_gating()
638 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
727 tmp = RREG32_PLL(R300_SCLK_CNTL2); in radeon_legacy_set_clock_gating()
731 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
876 tmp = RREG32_PLL(R300_SCLK_CNTL2); in radeon_legacy_set_clock_gating()
879 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
957 tmp = RREG32_PLL(R300_SCLK_CNTL2); in radeon_legacy_set_clock_gating()
961 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
H A Dradeon_reg.h1691 #define R300_SCLK_CNTL2 0x1e /* PLL */ macro