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Searched refs:RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT (Results 1 – 13 of 13) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7219 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a macro
H A Dgfx_7_2_sh_mask.h7744 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa macro
H A Dgfx_8_0_sh_mask.h8588 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa macro
H A Dgfx_8_1_sh_mask.h9146 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h22469 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT … macro
H A Dgc_9_1_sh_mask.h23760 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h23763 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h25946 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h17593 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h33247 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h32565 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h35733 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h31096 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT … macro