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Searched refs:RLC_SERDES_WR_CTRL__REG_ADDR_MASK (Results 1 – 10 of 10) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7296 #define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000L macro
H A Dgfx_7_2_sh_mask.h8053 #define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000 macro
H A Dgfx_8_0_sh_mask.h8963 #define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000 macro
H A Dgfx_8_1_sh_mask.h9505 #define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000 macro
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v8_0.c5510 RLC_SERDES_WR_CTRL__REG_ADDR_MASK | in gfx_v8_0_send_serdes_cmd()
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h23290 #define RLC_SERDES_WR_CTRL__REG_ADDR_MASK … macro
H A Dgc_9_1_sh_mask.h24581 #define RLC_SERDES_WR_CTRL__REG_ADDR_MASK … macro
H A Dgc_9_2_1_sh_mask.h24645 #define RLC_SERDES_WR_CTRL__REG_ADDR_MASK … macro
H A Dgc_9_4_3_sh_mask.h26904 #define RLC_SERDES_WR_CTRL__REG_ADDR_MASK … macro
H A Dgc_9_4_2_sh_mask.h22089 #define RLC_SERDES_WR_CTRL__REG_ADDR_MASK … macro