Searched refs:RREG32_PLL (Results 1 – 12 of 12) sorted by relevance
158 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & in radeon_read_clocks_OF()488 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_engine_clock()494 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()500 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()512 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()520 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()526 tmp = RREG32_PLL(RADEON_SPLL_CNTL); in radeon_legacy_set_engine_clock()532 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_engine_clock()566 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()631 tmp = RREG32_PLL(R300_SCLK_CNTL2); in radeon_legacy_set_clock_gating()[all …]
224 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); in radeon_pll_wait_for_read_update_complete()232 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); in radeon_pll_write_update()251 RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); in radeon_pll2_wait_for_read_update_complete()259 while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); in radeon_pll2_write_update()854 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & in radeon_set_pll()903 RREG32_PLL(RADEON_P2PLL_CNTL)); in radeon_set_pll()922 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_set_pll()934 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && in radeon_set_pll()935 (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) & in radeon_set_pll()1009 RREG32_PLL(RADEON_PPLL_CNTL)); in radeon_set_pll()
260 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH); in rs600_pm_misc()277 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL); in rs600_pm_misc()289 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL); in rs600_pm_misc()297 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL); in rs600_pm_misc()304 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL); in rs600_pm_misc()
1156 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); in radeon_legacy_get_lvds_info_from_regs()1161 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; in radeon_legacy_get_lvds_info_from_regs()3003 val = RREG32_PLL(reg); in radeon_combios_external_tmds_setup()3082 (RREG32_PLL in combios_parse_mmio_table()3132 tmp = RREG32_PLL(addr); in combios_parse_pll_table()3150 (RREG32_PLL in combios_parse_pll_table()3158 if (RREG32_PLL in combios_parse_pll_table()3166 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); in combios_parse_pll_table()3170 RREG32_PLL in combios_parse_pll_table()
480 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1)); in rv515_clock_startup()482 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1)); in rv515_clock_startup()484 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1)); in rv515_clock_startup()
199 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); in r420_clock_resume()
120 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_lvds_update()653 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_primary_dac_detect()1576 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_tv_dac_detect()
390 sclk_cntl = RREG32_PLL(SCLK_CNTL); in r100_pm_misc()391 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); in r100_pm_misc()393 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); in r100_pm_misc()2697 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); in r100_set_common_regs()3871 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); in r100_clock_startup()
285 save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL); in radeon_wait_pll_lock()
1362 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); in r300_clock_startup()
2558 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) macro2591 uint32_t tmp_ = RREG32_PLL(reg); \
1239 uint32_t tmp_ = RREG32_PLL(reg); \