1 /* $OpenBSD: rtl80x9reg.h,v 1.4 2014/11/24 02:03:37 brad Exp $ */ 2 /* $NetBSD: rtl80x9reg.h,v 1.2 1998/10/31 00:31:43 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Registers on Realtek 8019 and 8029 NE2000-compatible network interfaces. 36 * 37 * Data sheets for these chips can be found at: 38 * 39 * http://www.realtek.com.tw 40 */ 41 42 #ifndef _DEV_IC_RTL80x9_REG_H_ 43 #define _DEV_IC_RTL80x9_REG_H_ 44 45 /* 46 * Page 0 register offsets. 47 */ 48 #define NERTL_RTL0_8019ID0 0x0a /* 8019 ID Register 0 */ 49 #define RTL0_8019ID0 'P' 50 51 #define NERTL_RTL0_8019ID1 0x0b /* 8019 ID Register 1 */ 52 #define RTL0_8019ID1 'p' 53 54 /* 55 * Page 3 register offsets. 56 */ 57 #define NERTL_RTL3_EECR 0x01 /* EEPROM Command Register */ 58 #define RTL3_EECR_EEM1 0x80 /* EEPROM Operating Mode */ 59 #define RTL3_EECR_EEM0 0x40 60 /* 0 0 Normal operation */ 61 /* 0 1 Auto-load */ 62 /* 1 0 9346 programming */ 63 /* 1 1 Config register write enab */ 64 #define RTL3_EECR_EECS 0x08 /* EEPROM Chip Select */ 65 #define RTL3_EECR_EESK 0x04 /* EEPROM Clock */ 66 #define RTL3_EECR_EEDI 0x02 /* EEPROM Data In */ 67 #define RTL3_EECR_EEDO 0x01 /* EEPROM Data Out */ 68 69 #define NERTL_RTL3_BPAGE 0x02 /* BROM Page Register (8019) */ 70 71 #define NERTL_RTL3_CONFIG0 0x03 /* Configuration 0 (ro) */ 72 #define RTL3_CONFIG0_JP 0x08 /* jumper mode (8019) */ 73 #define RTL3_CONFIG0_BNC 0x04 /* BNC is active */ 74 75 #define NERTL_RTL3_CONFIG1 0x04 /* Configuration 1 (8019) */ 76 #define RTL3_CONFIG1_IRQEN 0x80 /* IRQ Enable */ 77 #define RTL3_CONFIG1_IRQS2 0x40 /* IRQ Select */ 78 #define RTL3_CONFIG1_IRQS1 0x20 79 #define RTL3_CONFIG1_IRQS0 0x10 80 /* 0 0 0 int 0 irq 2/9 */ 81 /* 0 0 1 int 1 irq 3 */ 82 /* 0 1 0 int 2 irq 4 */ 83 /* 0 1 1 int 3 irq 5 */ 84 /* 1 0 0 int 4 irq 10 */ 85 /* 1 0 1 int 5 irq 11 */ 86 /* 1 1 0 int 6 irq 12 */ 87 /* 1 1 1 int 7 irq 15 */ 88 #define RTL_CONFIG1_IOS3 0x08 /* I/O base Select */ 89 #define RTL_CONFIG1_IOS2 0x04 90 #define RTL_CONFIG1_IOS1 0x02 91 #define RTL_CONFIG1_IOS0 0x01 92 /* 0 0 0 0 0x300 */ 93 /* 0 0 0 1 0x320 */ 94 /* 0 0 1 0 0x340 */ 95 /* 0 0 1 1 0x360 */ 96 /* 0 1 0 0 0x380 */ 97 /* 0 1 0 1 0x3a0 */ 98 /* 0 1 1 0 0x3c0 */ 99 /* 0 1 1 1 0x3e0 */ 100 /* 1 0 0 0 0x200 */ 101 /* 1 0 0 1 0x220 */ 102 /* 1 0 1 0 0x240 */ 103 /* 1 0 1 1 0x260 */ 104 /* 1 1 0 0 0x280 */ 105 /* 1 1 0 1 0x2a0 */ 106 /* 1 1 1 0 0x2c0 */ 107 /* 1 1 1 1 0x2e0 */ 108 109 #define NERTL_RTL3_CONFIG2 0x05 /* Configuration 2 */ 110 #define RTL3_CONFIG2_PL1 0x80 /* Network media type */ 111 #define RTL3_CONFIG2_PL0 0x40 112 /* 0 0 TP/CX auto-detect */ 113 /* 0 1 10baseT */ 114 /* 1 0 10base5 */ 115 /* 1 1 10base2 */ 116 #define RTL3_CONFIG2_8029FCE 0x20 /* Flow Control Enable */ 117 #define RTL3_CONFIG2_8029PF 0x10 /* Pause Flag */ 118 #define RTL3_CONFIG2_8029BS1 0x02 /* Boot Rom Size */ 119 #define RTL3_CONFIG2_8029BS0 0x01 120 /* 0 0 No Boot Rom */ 121 /* 0 1 8k */ 122 /* 1 0 16k */ 123 /* 1 1 32k */ 124 #define RTL3_CONFIG2_8019BSELB 0x20 /* BROM disable */ 125 #define RTL3_CONFIG2_8019BS4 0x10 /* BROM size/base */ 126 #define RTL3_CONFIG2_8019BS3 0x08 127 #define RTL3_CONFIG2_8019BS2 0x04 128 #define RTL3_CONFIG2_8019BS1 0x02 129 #define RTL3_CONFIG2_8019BS0 0x01 130 131 #define NERTL_RTL3_CONFIG3 0x06 /* Configuration 3 */ 132 #define RTL3_CONFIG3_8019PNP 0x80 /* PnP Mode */ 133 #define RTL3_CONFIG3_FUDUP 0x40 /* Full Duplex */ 134 #define RTL3_CONFIG3_LEDS1 0x20 /* LED1/2 pin configuration */ 135 /* 0 LED1 == LED_RX, LED2 == LED_TX */ 136 /* 1 LED1 == LED_CRS, LED2 == MCSB */ 137 #define RTL3_CONFIG3_LEDS0 0x10 /* LED0 pin configuration */ 138 /* 0 LED0 pin == LED_COL */ 139 /* 1 LED0 pin == LED_LINK */ 140 #define RTL3_CONFIG3_SLEEP 0x04 /* Sleep mode */ 141 #define RTL3_CONFIG3_PWRDN 0x02 /* Power Down */ 142 #define RTL3_CONFIG3_8019ACTIVEB 0x01 /* inverse of bit 0 in PnP Act Reg */ 143 144 #define NERTL_RTL3_CSNSAV 0x08 /* CSN Save Register (8019) */ 145 146 #define NERTL_RTL3_HLTCLK 0x09 /* Halt Clock */ 147 #define RTL3_HLTCLK_RUNNING 'R' /* clock runs in power down */ 148 #define RTL3_HLTCLK_HALTED 'H' /* clock halted in power down */ 149 150 #define NERTL_RTL3_INTR 0x0b /* ISA bus states of INT7-0 (8019) */ 151 152 #define NERTL_RTL3_8029ID0 0x0e /* ID register 0 */ 153 154 #define NERTL_RTL3_8029ID1 0x0f /* ID register 1 */ 155 156 #endif /* _DEV_IC_RTL80x9_REG_H_ */ 157