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Searched refs:RegKind (Results 1 – 10 of 10) sorted by relevance

/openbsd/gnu/llvm/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp111 unsigned &RegKind);
1055 unsigned RegKind; in parseOperand() local
1114 unsigned RegKind; in parseSparcAsmOperand() local
1213 RegKind = SparcOperand::rk_None; in matchRegisterName()
1220 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
1226 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
1318 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
1325 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
1331 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
1337 RegKind = SparcOperand::rk_IntReg; in matchRegisterName()
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/openbsd/gnu/llvm/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp68 enum class RegKind { enum
276 template <RegKind RK>
378 RegKind Kind;
418 RegKind RegisterKind;
1229 RegKind RK; in isSVEPredicateAsCounterReg()
1245 RegKind RK; in isSVEVectorReg()
2193 assert((Kind == RegKind::NeonVector || Kind == RegKind::SVEDataVector || in CreateVectorReg()
2618 case RegKind::Matrix: in parseVectorKind()
2906 case RegKind::Scalar: in getNumRegsForRegKind()
2910 case RegKind::Matrix: in getNumRegsForRegKind()
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/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp122 unsigned RegKind : 4; member
193 Op->Mem.RegKind = RegKind; in createMem()
226 bool isReg(RegisterKind RegKind) const { in isReg()
227 return Kind == KindReg && Reg.Kind == RegKind; in isReg()
267 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const { in isMem()
268 return isMem(MemKind) && Mem.RegKind == RegKind; in isMem()
276 bool isMemDisp12Len4(RegisterKind RegKind) const { in isMemDisp12Len4()
279 bool isMemDisp12Len8(RegisterKind RegKind) const { in isMemDisp12Len8()
439 RegisterKind RegKind);
1112 RegisterKind RegKind) { in parseAddress() argument
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/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp1233 switch (RegKind) { in usesRegister()
2508 switch (RegKind) { in AddNextRegisterToList()
2633 assert(isRegularReg(RegKind)); in getRegularReg()
2636 if (RegKind == IS_SGPR || RegKind == IS_TTMP) { in getRegularReg()
2648 int RCID = getRegClass(RegKind, RegWidth); in getRegularReg()
2714 RegKind = IS_SPECIAL; in ParseSpecialReg()
2737 RegKind = RI->Kind; in ParseRegularReg()
2790 if (NextRegKind != RegKind) { in ParseRegList()
2803 if (isRegularReg(RegKind)) in ParseRegList()
2860 switch (RegKind) { in getGprCountSymbolName()
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/openbsd/gnu/llvm/lldb/source/Plugins/ABI/X86/
H A DABIX86.cpp38 enum RegKind { enum
52 RegKind subreg_kind;
/openbsd/gnu/llvm/llvm/tools/llvm-readobj/
H A DARMWinEHPrinter.cpp884 int RegKind = (OC[Offset + 2] & 0xC0) >> 6; in opcode_save_any_reg() local
891 if (!Writeback && !Paired && RegKind != 2) in opcode_save_any_reg()
905 if (RegKind == 0) in opcode_save_any_reg()
907 if ((OC[Offset + 1] & 0x80) == 0x80 || RegKind == 3 || Reg > MaxReg) { in opcode_save_any_reg()
926 if (RegKind == 1) { in opcode_save_any_reg()
928 } else if (RegKind == 2) { in opcode_save_any_reg()
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td556 let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
566 let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
909 let ParserMethod = "tryParseSVEPredicateVector<RegKind::SVEPredicateVector>";
936 let ParserMethod = "tryParseSVEPredicateVector<RegKind::SVEPredicateAsCounter>";
990 let ParserMethod = "tryParseVectorList<RegKind::SVEPredicateVector>";
991 let PredicateMethod = "isTypedVectorList<RegKind::SVEPredicateVector, "
1022 "isTypedVectorListMultiple<RegKind::SVEPredicateVector, " # NumRegs # ", 0, "
1148 let ParserMethod = "tryParseVectorList<RegKind::SVEDataVector>";
1150 "isTypedVectorList<RegKind::SVEDataVector, " #NumRegs #", 0, " #ElementWidth #">";
1247 "isTypedVectorListMultiple<RegKind::SVEDataVector, " # NumRegs # ", 0, "
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/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DGCNRegPressure.h31 enum RegKind { enum
/openbsd/gnu/llvm/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp454 bool validateMSAIndex(int Val, int RegKind);
809 enum RegKind { enum in __anon41cfaf1f0211::MipsOperand
867 RegKind Kind; /// Bitfield of the kinds it could possibly be
897 RegKind RegKind, in CreateReg() argument
904 Op->RegIdx.Kind = RegKind; in CreateReg()
/openbsd/gnu/llvm/llvm/lib/Transforms/Vectorize/
H A DLoopVectorize.cpp5224 TargetTransformInfo::RegisterKind RegKind = in getMaximizedVFForTarget() local
5229 TTI.shouldMaximizeVectorBandwidth(RegKind))) { in getMaximizedVFForTarget()