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Searched refs:SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK (Results 1 – 9 of 9) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_sh_mask.h1139 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK … macro
H A Dsdma0_4_0_sh_mask.h1147 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L macro
H A Dsdma0_4_2_sh_mask.h1151 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK … macro
H A Dsdma0_4_2_2_sh_mask.h1161 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/oss/
H A Doss_3_0_1_sh_mask.h1607 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 macro
H A Doss_3_0_sh_mask.h1929 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x4 macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_sh_mask.h931 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_sh_mask.h931 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h938 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK … macro