Home
last modified time | relevance | path

Searched refs:SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT (Results 1 – 13 of 13) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_sh_mask.h510 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT … macro
H A Dsdma0_4_0_sh_mask.h511 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c macro
H A Dsdma0_4_2_sh_mask.h511 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT … macro
H A Dsdma0_4_2_2_sh_mask.h517 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/oss/
H A Doss_2_0_sh_mask.h958 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c macro
H A Doss_2_4_sh_mask.h1042 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c macro
H A Doss_3_0_1_sh_mask.h1060 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c macro
H A Doss_3_0_sh_mask.h1566 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_sh_mask.h202 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_sh_mask.h187 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h219 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h195 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h220 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT … macro