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Searched refs:SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT (Results 1 – 9 of 9) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_sh_mask.h819 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT … macro
H A Dsdma0_4_0_sh_mask.h820 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 macro
H A Dsdma0_4_2_sh_mask.h836 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT … macro
H A Dsdma0_4_2_2_sh_mask.h842 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_sh_mask.h531 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_sh_mask.h529 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h538 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h549 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h503 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT … macro