Home
last modified time | relevance | path

Searched refs:SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK (Results 1 – 8 of 8) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_sh_mask.h1249 #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L macro
H A Dsdma1_4_2_2_sh_mask.h1261 #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK … macro
H A Dsdma1_4_2_sh_mask.h1253 #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/oss/
H A Doss_3_0_1_sh_mask.h2779 #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 macro
H A Doss_3_0_sh_mask.h2893 #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0xf0 macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_sh_mask.h3857 #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_sh_mask.h3807 #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK … macro
H A Dgc_10_3_0_sh_mask.h3970 #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK … macro