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Searched refs:SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK (Results 1 – 10 of 10) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_sh_mask.h1478 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L macro
H A Dsdma1_4_2_2_sh_mask.h1492 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK … macro
H A Dsdma1_4_2_sh_mask.h1484 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/oss/
H A Doss_2_0_sh_mask.h1661 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 macro
H A Doss_2_4_sh_mask.h1861 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 macro
H A Doss_3_0_1_sh_mask.h2807 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 macro
H A Doss_3_0_sh_mask.h2921 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_sh_mask.h4094 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_sh_mask.h4042 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h4215 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK … macro