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Searched refs:SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT (Results 1 – 5 of 5) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_2_2_sh_mask.h2871 #define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT … macro
H A Dsdma1_4_2_sh_mask.h2863 #define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_sh_mask.h5515 #define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_sh_mask.h5433 #define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h5676 #define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT … macro