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Searched refs:SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT (Results 1 – 12 of 12) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_sh_mask.h539 #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 macro
H A Dsdma1_4_2_2_sh_mask.h541 #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT … macro
H A Dsdma1_4_2_sh_mask.h537 #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/oss/
H A Doss_2_0_sh_mask.h1484 #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 macro
H A Doss_2_4_sh_mask.h1648 #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 macro
H A Doss_3_0_1_sh_mask.h2166 #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 macro
H A Doss_3_0_sh_mask.h2470 #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_sh_mask.h3044 #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_sh_mask.h2750 #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h3019 #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h2823 #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h3128 #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT … macro