1 /* $OpenBSD: satareg.h,v 1.3 2022/01/09 05:42:37 jsg Exp $ */ 2 /* $NetBSD: satareg.h,v 1.3 2004/05/23 23:07:59 wiz Exp $ */ 3 4 /*- 5 * Copyright (c) 2003 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of Wasabi Systems, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _DEV_ATA_SATAREG_H_ 34 #define _DEV_ATA_SATAREG_H_ 35 36 /* 37 * Serial ATA register definitions. 38 * 39 * Reference: 40 * 41 * Serial ATA: High Speed Serialized AT Attachment 42 * Revision 1.0 29-August-2001 43 * Serial ATA Working Group 44 */ 45 46 /* 47 * SStatus (SCR0) -- 48 * Serial ATA interface status register 49 */ 50 /* 51 * The DET value indicates the interface device detection and 52 * PHY state. 53 */ 54 #define SStatus_DET_NODEV (0x0 << 0) /* no device connected */ 55 #define SStatus_DET_DEV_NE (0x1 << 0) /* device, but PHY comm not 56 established */ 57 #define SStatus_DET_DEV (0x3 << 0) /* device, PHY comm 58 established */ 59 #define SStatus_DET_OFFLINE (0x4 << 0) /* PHY in offline mode */ 60 #define SStatus_DET_mask (0xf << 0) 61 #define SStatus_DET_shift 0 62 /* 63 * The SPD value indicates the negotiated interface communication 64 * speed established. 65 */ 66 #define SStatus_SPD_NONE (0x0 << 4) /* no negotiated speed */ 67 #define SStatus_SPD_G1 (0x1 << 4) /* Generation 1 (1.5Gb/s) */ 68 #define SStatus_SPD_G2 (0x2 << 4) /* Generation 2 (3.0Gb/s) */ 69 #define SStatus_SPD_mask (0xf << 4) 70 #define SStatus_SPD_shift 4 71 /* 72 * The IPM value indicates the current interface power management 73 * state. 74 */ 75 #define SStatus_IPM_NODEV (0x0 << 8) /* no device connected */ 76 #define SStatus_IPM_ACTIVE (0x1 << 8) /* ACTIVE state */ 77 #define SStatus_IPM_PARTIAL (0x2 << 8) /* PARTIAL pm state */ 78 #define SStatus_IPM_SLUMBER (0x6 << 8) /* SLUMBER pm state */ 79 #define SStatus_IPM_mask (0xf << 8) 80 #define SStatus_IPM_shift 8 81 82 /* 83 * SError (SCR1) -- 84 * Serial ATA interface error register 85 */ 86 #define SError_ERR_I (1U << 0) /* Recovered data integrity 87 error */ 88 #define SError_ERR_M (1U << 1) /* Recovered communications 89 error */ 90 #define SError_ERR_T (1U << 8) /* Non-recovered transient 91 data integrity error */ 92 #define SError_ERR_C (1U << 9) /* Non-recovered persistent 93 communication or data 94 integrity error */ 95 #define SError_ERR_P (1U << 10) /* Protocol error */ 96 #define SError_ERR_E (1U << 11) /* Internal error */ 97 #define SError_DIAG_N (1U << 16) /* PhyRdy change */ 98 #define SError_DIAG_I (1U << 17) /* PHY internal error */ 99 #define SError_DIAG_W (1U << 18) /* Comm Wake */ 100 #define SError_DIAG_B (1U << 19) /* 10b to 8b decode error */ 101 #define SError_DIAG_D (1U << 20) /* Disparity error */ 102 #define SError_DIAG_C (1U << 21) /* CRC error */ 103 #define SError_DIAG_H (1U << 22) /* Handshake error */ 104 #define SError_DIAG_S (1U << 23) /* Link sequence error */ 105 #define SError_DIAG_T (1U << 24) /* Transport state transition 106 error */ 107 #define SError_DIAG_F (1U << 25) /* Unrecognized FIS type */ 108 #define SError_DIAG_X (1U << 26) /* Device Exchanged */ 109 110 /* 111 * SControl (SCR2) -- 112 * Serial ATA interface control register 113 */ 114 /* 115 * The DET field controls the host adapter device detection 116 * and interface initialization. 117 */ 118 #define SControl_DET_NONE (0x0 << 0) /* No device detection or 119 initialization action 120 requested */ 121 #define SControl_DET_INIT (0x1 << 0) /* Initialize interface 122 communication (equiv 123 of a hard reset) */ 124 #define SControl_DET_DISABLE (0x4 << 0) /* disable interface and 125 take PHY offline */ 126 /* 127 * The SPD field represents the highest allowed communication 128 * speed the interface is allowed to negotiate when communication 129 * is established. 130 */ 131 #define SControl_SPD_ANY (0x0 << 4) /* No restrictions */ 132 #define SControl_SPD_G1 (0x1 << 4) /* Generation 1 (1.5Gb/s) */ 133 #define SControl_SPD_G2 (0x2 << 4) /* Generation 2 (3.0Gb/s) */ 134 /* 135 * The IPM field represents the enabled interface power management 136 * states that can be invoked via the Serial ATA interface power 137 * management capabilities. 138 */ 139 #define SControl_IPM_ANY (0x0 << 8) /* No restrictions */ 140 #define SControl_IPM_NOPARTIAL (0x1 << 8) /* PARTIAL disabled */ 141 #define SControl_IPM_NOSLUMBER (0x2 << 8) /* SLUMBER disabled */ 142 #define SControl_IPM_NONE (0x3 << 8) /* No power management */ 143 /* 144 * The SPM field selects a power management state. A non-zero 145 * value written to this field causes initiation of the selected 146 * power management state. 147 */ 148 #define SControl_SPM_PARTIAL (0x1 << 12) /* transition to PARTIAL */ 149 #define SControl_SPM_SLUMBER (0x2 << 12) /* transition to SLUBMER */ 150 #define SControl_SPM_ComWake (0x4 << 12) /* transition from PM */ 151 /* 152 * The PMP field identifies the selected Port Multiplier Port 153 * for accessing the SActive register. 154 */ 155 #define SControl_PMP(x) ((x) << 16) 156 157 #endif /* _DEV_ATA_SATAREG_H_ */ 158