Searched refs:SMRD (Results 1 – 15 of 15) sorted by relevance
82 int checkSMRDHazards(MachineInstr *SMRD);
38 let SMRD = 1;67 let SMRD = ps.SMRD;289 // SMRD instructions, because the SReg_32_XM0 register class does not include M0290 // and writing to M0 from an SMRD instruction will hang the GPU.293 // does sdst for SMRD on SI/CI?305 // FIXME: exec_lo/exec_hi appear to be allowed for SMRD loads on907 // Global and constant loads can be selected to either MUBUF or SMRD908 // instructions, but SMRD instructions are faster so we want the instruction
60 SIInstrFlags::SMRD | SIInstrFlags::DS |
41 field bit SMRD = 0;179 let TSFlags{19} = SMRD;
483 return MI.getDesc().TSFlags & SIInstrFlags::SMRD; in isSMRD()487 return get(Opcode).TSFlags & SIInstrFlags::SMRD; in isSMRD()711 return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD); in isScalarUnit()
666 int GCNHazardRecognizer::checkSMRDHazards(MachineInstr *SMRD) { in checkSMRDHazards() argument669 WaitStatesNeeded = checkSoftClauseHazards(SMRD); in checkSMRDHazards()685 bool IsBufferSMRD = TII.isBufferSMRD(*SMRD); in checkSMRDHazards()687 for (const MachineOperand &Use : SMRD->uses()) { in checkSMRDHazards()
56 SMRD = 1 << 19, enumerator
757 // Subset of SReg_32 without M0 for SMRD instructions and alike.
282 } else if (MCID.TSFlags & SIInstrFlags::SMRD) { in generateWaitCntInfo()
209 !(MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SMRD)) ? " sc0" in printCPol()
612 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { in getInstruction()
1017 SMRD/SMEM Modifiers
14451 SMRD/SMEM
4151 if ((TSFlags & SIInstrFlags::SMRD) == 0) in validateSMEMOffset()4508 if (TSFlags & SIInstrFlags::SMRD) { in validateCoherencyBits()
422 SMRD section in Instructions