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Searched refs:SOC15_REG_ENTRY (Results 1 – 15 of 15) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v9_4.c52 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1 },
58 { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1 },
60 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 8, 16 },
132 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
136 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
140 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
144 SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
176 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
180 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
184 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
[all …]
H A Dmmhub_v9_4.c1535 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 0, 0, 0 },
1536 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 0, 0, 0 },
1537 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 0, 0, 0 },
1538 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 0, 0, 0 },
1539 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 0, 0, 0 },
1541 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 0, 0, 0 },
1544 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 0, 0, 0 },
1547 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 0, 0, 0 },
1550 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 0, 0, 0 },
1553 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 0, 0, 0 },
[all …]
H A Dgfx_v9_4_2.c899 SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT),
903 SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT),
907 SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT),
911 SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT),
932 SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
936 SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
940 SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
944 SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
948 SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
951 SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
[all …]
H A Dmmhub_v1_7.c1186 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), 0, 0, 0 },
1187 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), 0, 0, 0 },
1188 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), 0, 0, 0 },
1189 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), 0, 0, 0 },
1190 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), 0, 0, 0 },
1191 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), 0, 0, 0 },
1192 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), 0, 0, 0 },
1193 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), 0, 0, 0 },
1195 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), 0, 0, 0 },
1198 { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), 0, 0, 0 },
[all …]
H A Dsdma_v4_4.c60 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
64 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
68 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
72 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
76 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
80 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
84 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
124 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
128 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
132 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),
[all …]
H A Dmmhub_v1_0.c591 { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
595 { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
607 { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
611 { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
651 { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
655 { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
667 { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
702 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 0, 0, 0},
703 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), 0, 0, 0},
704 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 0, 0, 0},
[all …]
H A Dgfx_v9_0.c718 {SOC15_REG_ENTRY(GC, 0, mmGRBM_GFX_INDEX)},
719 {SOC15_REG_ENTRY(GC, 0, mmSQ_IND_INDEX)},
6029 { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT),
6042 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
6047 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
6052 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
6057 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
6062 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
6067 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
6219 { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
[all …]
H A Dsoc21.c250 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},
251 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},
252 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
253 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},
254 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},
255 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},
258 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)},
259 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},
264 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},
267 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
[all …]
H A Dnv.c337 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
338 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
339 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
340 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
341 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
342 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
345 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
346 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
351 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
354 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
[all …]
H A Dsoc15.c358 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
359 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
360 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
361 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
362 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
363 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
366 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
372 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
375 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
376 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
[all …]
H A Dsdma_v4_0.c296 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
300 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
304 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
308 { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
316 { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
320 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
324 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
328 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
332 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
336 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
[all …]
H A Dsoc15.h89 #define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg macro
H A Dgfx_v9_4_3.c1343 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)},
1344 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)},
3759 SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16
/openbsd/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_baco.c36 {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIF_FB_EN), 0, 0, 0, 0},
43 …{CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_EN_MASK, BACO_CNTL__B…
45 …{CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_DUMMY_EN_MASK, BACO_C…
52 …{CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_POWER_OFF_MASK, BACO_…
56 …{CMD_WAITFOR, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_MODE_MASK, BACO_CNTL__BACO_MO…
60 …{CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_POWER_OFF_MASK, BACO_…
71 …{CMD_WAITFOR, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_EXIT_MASK, 0, 0xffffff…
75 …{CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_EN_MASK, BACO_CNTL__B…
76 {CMD_WAITFOR, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0}
80 {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0},
[all …]
H A Dvega20_baco.c35 {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0},
36 {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_7), 0, 0, 0, 0},