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Searched refs:SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK (Results 1 – 7 of 7) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/smu/
H A Dsmu_6_0_sh_mask.h298 #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x00000001L macro
H A Dsmu_7_0_0_sh_mask.h207 #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 macro
H A Dsmu_7_1_1_sh_mask.h197 #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 macro
H A Dsmu_7_0_1_sh_mask.h199 #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 macro
H A Dsmu_7_1_0_sh_mask.h197 #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 macro
H A Dsmu_7_1_2_sh_mask.h199 #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 macro
H A Dsmu_7_1_3_sh_mask.h225 #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 macro