Home
last modified time | relevance | path

Searched refs:SPR (Results 1 – 25 of 40) sorted by relevance

12

/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMInstrVFP.td2039 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2063 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
2080 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2104 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
2120 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2172 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2213 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2237 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
2265 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2317 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
[all …]
H A DARMInstrCDE.td487 def cde_vcx_s_regs : CDE_VCX_RegisterOperandsTemplate<SPR>;
551 (f32 (CDE_VCX1A_fpsp p_imm:$coproc, SPR:$acc, imm_11b:$imm))>;
557 def : Pat<(f32 (int_arm_cde_vcx2 timm:$coproc, (f32 SPR:$n), timm:$imm)),
558 (f32 (CDE_VCX2_fpsp p_imm:$coproc, SPR:$n, imm_6b:$imm))>;
559 def : Pat<(f32 (int_arm_cde_vcx2a timm:$coproc, (f32 SPR:$acc), (f32 SPR:$n),
561 (f32 (CDE_VCX2A_fpsp p_imm:$coproc, SPR:$acc, SPR:$n, imm_6b:$imm))>;
568 def : Pat<(f32 (int_arm_cde_vcx3 timm:$coproc, (f32 SPR:$n), (f32 SPR:$m),
570 (f32 (CDE_VCX3_fpsp p_imm:$coproc, (f32 SPR:$n), (f32 SPR:$m),
572 def : Pat<(f32 (int_arm_cde_vcx3a timm:$coproc, (f32 SPR:$acc), (f32 SPR:$n),
573 (f32 SPR:$m), timm:$imm)),
[all …]
H A DARMRegisterInfo.td412 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
413 let AltOrders = [(add (decimate SPR, 2), SPR),
414 (add (decimate SPR, 4),
415 (decimate SPR, 2),
416 (decimate (rotl SPR, 1), 4),
417 (decimate (rotl SPR, 1), 2))];
425 let AltOrders = [(add (decimate HPR, 2), SPR),
436 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
461 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
466 // 32-bit SPR subregs).
[all …]
H A DARMRegisterBanks.td13 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
H A DARMInstrNEON.td5264 def VFMALD : N3VCP8F16Q0<"vfmal", DPR, SPR, SPR, 0b00, 0b10, 1>;
5265 def VFMSLD : N3VCP8F16Q0<"vfmsl", DPR, SPR, SPR, 0b01, 0b10, 1>;
6732 def : Pat<(v2f32 (ARMvdup (f32 SPR:$src))),
6735 def : Pat<(v4f32 (ARMvdup (f32 SPR:$src))),
7397 : NEONFPPat<(f32 (OpNode SPR:$a)),
7405 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
7410 SPR:$a, ssub_0),
7427 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
7432 SPR:$acc, ssub_0),
7435 SPR:$a, ssub_0),
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td51 // SPR - One of the 32-bit special-purpose registers
52 class SPR<bits<10> num, string n> : PPCReg<n> {
248 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
250 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
253 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
254 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
257 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
260 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
262 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
265 // (which really is SPR register 1); this is the only bit interesting to a
[all …]
H A DPPCInstrFormats.td1612 bits<10> SPR;
1615 let Inst{11} = SPR{4};
1616 let Inst{12} = SPR{3};
1617 let Inst{13} = SPR{2};
1618 let Inst{14} = SPR{1};
1619 let Inst{15} = SPR{0};
1620 let Inst{16} = SPR{9};
1621 let Inst{17} = SPR{8};
1622 let Inst{18} = SPR{7};
1632 let SPR = spr;
[all …]
H A DPPCInstr64Bit.td557 def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR),
558 "mfspr $RT, $SPR", IIC_SprMFSPR>;
559 def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT),
560 "mtspr $SPR, $RT", IIC_SprMTSPR>;
564 // 64-bit SPR manipulation instrs.
1978 def : Pat<(i64 (int_ppc_mfspr timm:$SPR)),
1979 (MFSPR8 $SPR)>;
1980 def : Pat<(int_ppc_mtspr timm:$SPR, g8rc:$RT),
1981 (MTSPR8 $SPR, $RT)>;
H A DPPCInstrInfo.td2574 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2575 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2577 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2579 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2580 "mftb $RT, $SPR", IIC_SprMFTB>;
2583 "mfpmr $RT, $SPR", IIC_SprMFPMR>;
2586 "mtpmr $SPR, $RT", IIC_SprMTPMR>;
5168 def : Pat<(i32 (int_ppc_mfspr timm:$SPR)),
5169 (MFSPR $SPR)>;
5170 def : Pat<(int_ppc_mtspr timm:$SPR, gprc:$RT),
[all …]
H A DPPC.td228 "Target supports move to SPR with branch fusion",
H A DP9InstrResources.td935 (instregex "MF(SPR|CTR|LR)(8)?$"),
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86PartialReduction.cpp236 auto SPR = matchSelectPattern(SI, LHS, RHS); in trySADReplacement() local
237 if (SPR.Flavor != SPF_ABS) in trySADReplacement()
/openbsd/gnu/llvm/llvm/lib/Analysis/
H A DLazyValueInfo.cpp830 SelectPatternResult SPR = matchSelectPattern(SI, LHS, RHS); in solveBlockValueSelect() local
833 if (SelectPatternResult::isMinOrMax(SPR.Flavor) && in solveBlockValueSelect()
837 switch (SPR.Flavor) { in solveBlockValueSelect()
855 if (SPR.Flavor == SPF_ABS) { in solveBlockValueSelect()
864 if (SPR.Flavor == SPF_NABS) { in solveBlockValueSelect()
H A DValueTracking.cpp6157 SelectPatternResult SPR = matchClamp(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal); in matchMinMax() local
6158 if (SPR.Flavor != SelectPatternFlavor::SPF_UNKNOWN) in matchMinMax()
6159 return SPR; in matchMinMax()
6161 SPR = matchMinMaxOfMinMax(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal, Depth); in matchMinMax()
6162 if (SPR.Flavor != SelectPatternFlavor::SPF_UNKNOWN) in matchMinMax()
6163 return SPR; in matchMinMax()
/openbsd/gnu/gcc/gcc/config/rs6000/
H A D7450.md33 ;; MCIU performs imul and idiv, cr logical, SPR moves
H A Dpower5.md227 ; SPR move only executes in first IU.
H A Dpower4.md274 ; SPR move only executes in first IU.
/openbsd/gnu/usr.bin/binutils/opcodes/
H A Dppc-opc.c453 #define SPR SISIGNOPT + 1 macro
454 #define PMR SPR
459 #define SPRBAT SPR + 1
3577 { "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3776 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3889 { "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
4058 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
/openbsd/gnu/usr.bin/binutils-2.17/opcodes/
H A Dppc-opc.c463 #define SPR SISIGNOPT + 1 macro
464 #define PMR SPR
469 #define SPRBAT SPR + 1
3682 { "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3877 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3990 { "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
4159 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
/openbsd/gnu/usr.bin/binutils/gas/
H A DNEWS210 can be used any time. PowerPC 860 move to/from SPR instructions have been
/openbsd/gnu/llvm/llvm/lib/Transforms/InstCombine/
H A DInstCombineSelect.cpp3272 SelectPatternResult SPR = matchSelectPattern(&SI, LHS, RHS, &CastOp); in visitSelectInst() local
3273 auto SPF = SPR.Flavor; in visitSelectInst()
3298 CmpInst::Predicate MinMaxPred = getMinMaxPred(SPF, SPR.Ordered); in visitSelectInst()
H A DInstCombineCompares.cpp6222 SelectPatternResult SPR = matchSelectPattern(SI, A, B); in visitICmpInst() local
6223 if (SPR.Flavor != SPF_UNKNOWN) in visitICmpInst()
6887 SelectPatternResult SPR = matchSelectPattern(SI, A, B); in visitFCmpInst() local
6888 if (SPR.Flavor != SPF_UNKNOWN) in visitFCmpInst()
/openbsd/gnu/usr.bin/binutils-2.17/cpu/
H A Dfrv.cpu234 ; SPR Move to GR unit
235 (unit u-spr2gr "SPR Move to GR Unit" ()
242 ; GR Move to SPR unit
243 (unit u-gr2spr "GR Move to SPR Unit" ()
679 ; SPR Move to GR unit
680 (unit u-spr2gr "SPR Move to GR Unit" ()
695 ; GR Move to SPR unit
1102 ; SPR Move to GR unit
1118 ; GR Move to SPR unit
1479 ; SPR Move to GR unit
[all …]
/openbsd/gnu/usr.bin/binutils-2.17/gas/
H A DNEWS280 can be used any time. PowerPC 860 move to/from SPR instructions have been
/openbsd/gnu/usr.bin/binutils/cpu/
H A Dfrv.cpu234 ; SPR Move to GR unit
235 (unit u-spr2gr "SPR Move to GR Unit" ()
242 ; GR Move to SPR unit
243 (unit u-gr2spr "GR Move to SPR Unit" ()
679 ; SPR Move to GR unit
680 (unit u-spr2gr "SPR Move to GR Unit" ()
695 ; GR Move to SPR unit
696 (unit u-gr2spr "GR Move to SPR Unit" ()
1102 ; SPR Move to GR unit
1103 (unit u-spr2gr "SPR Move to GR Unit" ()
[all …]

12