| /openbsd/gnu/llvm/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMatInt.cpp | 25 case RISCV::SRLI: in getInstSeqCost()
214 TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros); in generateInstSeq()
224 TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros); in generateInstSeq()
403 case RISCV::SRLI: in getOpndKind()
|
| /openbsd/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 811 SDNode *SRLI = CurDAG->getMachineNode( in Select() local
812 RISCV::SRLI, DL, VT, SDValue(SLLI, 0), in Select()
814 ReplaceNode(Node, SRLI); in Select()
934 SDNode *SRLI = CurDAG->getMachineNode( in Select() local
937 ReplaceNode(Node, SRLI); in Select()
967 ReplaceNode(Node, SRLI); in Select()
980 unsigned SrliOpc = RISCV::SRLI; in Select()
988 SDNode *SRLI = CurDAG->getMachineNode( in Select() local
1017 SDNode *SRLI = CurDAG->getMachineNode( in Select() local
1018 RISCV::SRLI, DL, VT, X, in Select()
[all …]
|
| H A D | RISCVAsmPrinter.cpp | 306 OutStreamer->emitInstruction(MCInstBuilder(RISCV::SRLI) in EmitHwasanMemaccessSymbols()
322 MCInstBuilder(RISCV::SRLI).addReg(RISCV::X7).addReg(Reg).addImm(56), in EmitHwasanMemaccessSymbols()
|
| H A D | RISCVInstrInfoZb.td | 757 // Match a shifted 0xffffffff mask. Use SRLI to clear the LSBs and SLLI_UW to
760 (SLLI_UW (SRLI GPR:$rs1, Shifted32OnesMask:$mask),
796 // Use SRLI to clear the LSBs and SHXADD_UW to mask and shift.
798 (SH1ADD_UW (SRLI GPR:$rs1, 1), GPR:$rs2)>;
800 (SH2ADD_UW (SRLI GPR:$rs1, 2), GPR:$rs2)>;
802 (SH3ADD_UW (SRLI GPR:$rs1, 3), GPR:$rs2)>;
|
| H A D | RISCVSExtWRemoval.cpp | 78 case RISCV::SRLI: in isSignExtendingOpW()
|
| H A D | RISCVInstrInfo.td | 658 def SRLI : Shift_ri<0b00000, 0b101, "srli">;
1044 (SRLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
1241 def : PatGprUimmLog2XLen<srl, SRLI>;
1261 (SLLI (SRLI $rs, LeadingOnesMask:$mask), LeadingOnesMask:$mask)>;
1263 (SRLI (SLLI $rs, TrailingOnesMask:$mask), TrailingOnesMask:$mask)>;
1713 def : Pat<(i64 (and GPR:$rs1, 0xffffffff)), (SRLI (SLLI GPR:$rs1, 32), 32)>;
1718 (SRLI (SLLI GPR:$rs1, 32), (ImmSubFrom32 uimm5:$shamt))>;
|
| H A D | RISCVRegisterInfo.cpp | 736 case RISCV::SRLI: in getRegAllocationHints()
|
| H A D | RISCVFrameLowering.cpp | 586 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR) in emitPrologue()
|
| H A D | RISCVInstrInfoC.td | 828 def : CompressPat<(SRLI GPRC:$rs1, GPRC:$rs1, uimmlog2xlennonzero:$imm),
|
| H A D | RISCVInstrInfo.cpp | 2619 case RISCV::SRLI: { in hasAllNBitUsers()
|
| /openbsd/gnu/llvm/lldb/source/Plugins/Instruction/RISCV/ |
| H A D | RISCVInstructions.h | 143 R_SHAMT_TYPE_INST(SRLI);
278 LWU, LD, SD, SLLI, SRLI, SRAI, ADDIW, SLLIW, SRLIW, SRAIW, ADDW, SUBW, SLLW,
|
| H A D | RISCVCInstructions.h | 241 return SRLI{rd, rd, uint8_t(shamt)}; in DecodeC_SRLI()
|
| H A D | EmulateInstructionRISCV.cpp | 444 {"SRLI", 0xF800707F, 0x5013, DecodeRShamtType<SRLI>},
869 bool operator()(SRLI inst) { in operator ()()
|
| /openbsd/gnu/llvm/lld/ELF/Arch/ |
| H A D | RISCV.cpp | 59 SRLI = 0x5013, enumerator
225 write32le(buf + 20, itype(SRLI, X_T1, X_T1, config->is64 ? 1 : 2)); in writePltHeader()
|
| /openbsd/gnu/llvm/llvm/lib/Target/Xtensa/ |
| H A D | XtensaInstrInfo.td | 158 def SRLI : RRR_Inst<0x00, 0x01, 0x04, (outs AR:$r), (ins AR:$t, uimm4:$sa),
|
| /openbsd/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | MipsScheduleP5600.td | 438 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SRL|SRLI)_[BHWD]$")>;
|
| H A D | MipsScheduleGeneric.td | 1559 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SRL|SRLI)_[BHWD]$")>;
|
| /openbsd/gnu/llvm/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 2482 unsigned SecondOpcode = SignExtend ? RISCV::SRAI : RISCV::SRLI; in emitPseudoExtend()
|
| /openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 5651 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { in visitANDLike() local
5657 APInt SRLC = SRLI->getAPIntValue(); in visitANDLike()
|