1 /* $OpenBSD: stp4020reg.h,v 1.7 2008/06/26 05:42:18 ray Exp $ */ 2 /* $NetBSD: stp4020reg.h,v 1.1 1998/11/22 22:14:35 pk Exp $ */ 3 4 /*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 34 #ifndef _STP4020_REG_H 35 #define _STP4020_REG_H 36 37 /* 38 * STP4020: SBus/PCMCIA bridge supporting one Type-3 PCMCIA card, or up to 39 * two Type-1 and Type-2 PCMCIA cards.. 40 * Programming information source: 41 * - http://www.sun.com/microelectronics/datasheets/stp4020/ 42 * - SunOS 5.5 header file 43 */ 44 45 /* 46 * General chip attributes. 47 */ 48 #define STP4020_NSOCK 2 /* number of PCCARD sockets per STP4020 */ 49 #define STP4020_NWIN 3 /* number of windows per socket */ 50 51 /* 52 * Socket control registers. 53 * 54 * Each PCMCIA socket has two interface control registers and two interface 55 * status registers associated with it. 56 */ 57 58 /* 59 * Socket Interface Control register 0 60 */ 61 #define STP4020_ICR0_rsvd1 0xc000 /* reserved bits */ 62 #define STP4020_ICR0_PROMEN 0x2000 /* FCode PROM enable */ 63 /* Status change interrupts can be routed to one of two SBus interrupt levels:*/ 64 #define STP4020_ICR0_SCILVL 0x1000 /* card status change interrupt level */ 65 #define STP4020_ICR0_SCILVL_SB0 0x0000 /* interrupt on *SB_INT[0] */ 66 #define STP4020_ICR0_SCILVL_SB1 0x1000 /* interrupt on *SB_INT[1] */ 67 /* Interrupt enable bits: */ 68 #define STP4020_ICR0_CDIE 0x0800 /* card detect interrupt enable */ 69 #define STP4020_ICR0_BVD2IE 0x0400 /* battery voltage detect 2 int en. */ 70 #define STP4020_ICR0_BVD1IE 0x0200 /* battery voltage detect 1 int en. */ 71 #define STP4020_ICR0_RDYIE 0x0100 /* ready/busy interrupt enable */ 72 #define STP4020_ICR0_WPIE 0x0080 /* write protect interrupt enable */ 73 #define STP4020_ICR0_CTOIE 0x0040 /* PC card timeout interrupt enable */ 74 #define STP4020_ICR0_rsvd2 0x0020 /* */ 75 #define STP4020_ICR0_IOIE 0x0010 /* I/O (*IRQ) interrupt enable */ 76 /* PC card I/O interrupts can also be routed to one of two SBus intr levels: */ 77 #define STP4020_ICR0_IOILVL 0x0008 /* I/O (*IRQ) interrupt level (SBus) */ 78 #define STP4020_ICR0_IOILVL_SB0 0x0000 /* interrupt on *SB_INT[0] */ 79 #define STP4020_ICR0_IOILVL_SB1 0x0008 /* interrupt on *SB_INT[1] */ 80 81 #define STP4020_ICR0_SPKREN 0x0004 /* *SPKR_OUT enable */ 82 #define STP4020_ICR0_RESET 0x0002 /* PC card reset */ 83 #define STP4020_ICR0_IFTYPE 0x0001 /* PC card interface type */ 84 #define STP4020_ICR0_IFTYPE_MEM 0x0000 /* MEMORY only */ 85 #define STP4020_ICR0_IFTYPE_IO 0x0001 /* MEMORY and I/O */ 86 #define STP4020_ICR0_BITS "\010\1IFTYPE\2RESET\3SPKREN\4IOILVL\5IOIE" \ 87 "\7CTOIE\10WPIE\11RDYIE\12BVD1IE\13BVD2IE\14CDIE\15SCILV\16PROMEN" 88 89 /* Shorthand for all status change interrupts enables */ 90 #define STP4020_ICR0_ALL_STATUS_IE ( \ 91 STP4020_ICR0_CDIE | \ 92 STP4020_ICR0_BVD2IE | \ 93 STP4020_ICR0_BVD1IE | \ 94 STP4020_ICR0_RDYIE | \ 95 STP4020_ICR0_WPIE | \ 96 STP4020_ICR0_CTOIE \ 97 ) 98 99 /* 100 * Socket Interface Control register 1 101 */ 102 #define STP4020_ICR1_LPBKEN 0x8000 /* PC card data loopback enable */ 103 #define STP4020_ICR1_CD1DB 0x4000 /* card detect 1 diagnostic bit */ 104 #define STP4020_ICR1_BVD2DB 0x2000 /* battery voltage detect 2 diag bit */ 105 #define STP4020_ICR1_BVD1DB 0x1000 /* battery voltage detect 1 diag bit */ 106 #define STP4020_ICR1_RDYDB 0x0800 /* ready/busy diagnostic bit */ 107 #define STP4020_ICR1_WPDB 0x0400 /* write protect diagnostic bit */ 108 #define STP4020_ICR1_WAITDB 0x0200 /* *WAIT diagnostic bit */ 109 #define STP4020_ICR1_DIAGEN 0x0100 /* diagnostic enable bit */ 110 #define STP4020_ICR1_rsvd1 0x0080 /* reserved */ 111 #define STP4020_ICR1_APWREN 0x0040 /* PC card auto power switch enable */ 112 113 /* 114 * The Vpp controls are two-bit fields which specify which voltage 115 * should be switched onto Vpp for this socket. 116 * 117 * Both of the "no connect" states are equal. 118 */ 119 #define STP4020_ICR1_VPP2EN 0x0030 /* Vpp2 power enable */ 120 #define STP4020_ICR1_VPP2_OFF 0x0000 /* no connect */ 121 #define STP4020_ICR1_VPP2_VCC 0x0010 /* Vcc switched onto Vpp2 */ 122 #define STP4020_ICR1_VPP2_VPP 0x0020 /* Vpp switched onto Vpp2 */ 123 #define STP4020_ICR1_VPP2_ZIP 0x0030 /* no connect */ 124 125 #define STP4020_ICR1_VPP1EN 0x000c /* Vpp1 power enable */ 126 #define STP4020_ICR1_VPP1_OFF 0x0000 /* no connect */ 127 #define STP4020_ICR1_VPP1_VCC 0x0004 /* Vcc switched onto Vpp1 */ 128 #define STP4020_ICR1_VPP1_VPP 0x0008 /* Vpp switched onto Vpp1 */ 129 #define STP4020_ICR1_VPP1_ZIP 0x000c /* no connect */ 130 131 #define STP4020_ICR1_MSTPWR 0x0002 /* PC card master power enable */ 132 #define STP4020_ICR1_PCIFOE 0x0001 /* PC card interface output enable */ 133 134 #define STP4020_ICR1_BITS "\010\1PCIFOE\2MSTPWR\7APWREN\11DIAGEN" \ 135 "\12WAITDB\13WPDB\14RDYDB\15BVD1D\16BVD2D\17CD1DB\18LPBKEN" 136 137 /* 138 * Socket Interface Status register 0 139 * 140 * Some signals in this register change meaning depending on whether 141 * the socket is configured as MEMORY-ONLY or MEMORY & I/O: 142 * mo: valid only if the socket is in memory-only mode 143 * io: valid only if the socket is in memory and I/O mode. 144 * 145 * Pending interrupts are cleared by writing the corresponding status 146 * bit set in the upper half of this register. 147 */ 148 #define STP4020_ISR0_ZERO 0x8000 /* always reads back as zero (mo) */ 149 #define STP4020_ISR0_IOINT 0x8000 /* PC card I/O intr (*IRQ) posted (io)*/ 150 #define STP4020_ISR0_SCINT 0x4000 /* status change interrupt posted */ 151 #define STP4020_ISR0_CDCHG 0x2000 /* card detect status change */ 152 #define STP4020_ISR0_BVD2CHG 0x1000 /* battery voltage detect 2 status change */ 153 #define STP4020_ISR0_BVD1CHG 0x0800 /* battery voltage detect 1 status change */ 154 #define STP4020_ISR0_RDYCHG 0x0400 /* ready/busy status change */ 155 #define STP4020_ISR0_WPCHG 0x0200 /* write protect status change */ 156 #define STP4020_ISR0_PCTO 0x0100 /* PC card access timeout */ 157 #define STP4020_ISR0_ALL_STATUS_IRQ 0x7f00 158 159 #define STP4020_ISR0_LIVE 0x00ff /* live status bit mask */ 160 #define STP4020_ISR0_CD2ST 0x0080 /* card detect 2 live status */ 161 #define STP4020_ISR0_CD1ST 0x0040 /* card detect 1 live status */ 162 #define STP4020_ISR0_BVD2ST 0x0020 /* battery voltage detect 2 live status (mo) */ 163 #define STP4020_ISR0_SPKR 0x0020 /* SPKR signal live status (io)*/ 164 #define STP4020_ISR0_BVD1ST 0x0010 /* battery voltage detect 1 live status (mo) */ 165 #define STP4020_ISR0_STSCHG 0x0010 /* I/O *STSCHG signal live status (io)*/ 166 #define STP4020_ISR0_RDYST 0x0008 /* ready/busy live status (mo) */ 167 #define STP4020_ISR0_IOREQ 0x0008 /* I/O *REQ signal live status (io) */ 168 #define STP4020_ISR0_WPST 0x0004 /* write protect live status (mo) */ 169 #define STP4020_ISR0_IOIS16 0x0004 /* IOIS16 signal live status (io) */ 170 #define STP4020_ISR0_WAITST 0x0002 /* wait signal live status */ 171 #define STP4020_ISR0_PWRON 0x0001 /* PC card power status */ 172 173 #define STP4020_ISR0_IOBITS "\010\1PWRON\2WAITST\3IOIS16\4IOREQ" \ 174 "\5STSCHG\6SPKR\7CD1ST\10CD2ST\11PCTO\12WPCHG\13RDYCHG\14BVD1CHG" \ 175 "\15BVD2CHG\16CDCHG\17SCINT\20IOINT" 176 #define STP4020_ISR0_MOBITS "\010\1PWRON\2WAITST\3WPST\4RDYST" \ 177 "\5BVD1ST\6BVD2ST\7CD1ST\10CD2ST\11PCTO\12WPCHG\13RDYCHG\14BVD1CHG" \ 178 "\15BVD2CHG\16CDCHG\17SCINT" 179 180 /* 181 * Socket Interface Status register 1 182 */ 183 #define STP4020_ISR1_rsvd 0xffc0 /* reserved */ 184 #define STP4020_ISR1_PCTYPE_M 0x0030 /* PC card type(s) supported bit mask */ 185 #define STP4020_ISR1_PCTYPE_S 4 /* PC card type(s) supported bit shift */ 186 #define STP4020_ISR1_REV_M 0x000f /* ASIC revision level bit mask */ 187 #define STP4020_ISR1_REV_S 0 /* ASIC revision level bit shift */ 188 189 190 /* 191 * Socket window control/status register definitions. 192 * 193 * According to SunOS 5.5: 194 * "Each PCMCIA socket has three windows associated with it; each of 195 * these windows can be programmed to map in either the AM, CM or IO 196 * space on the PC card. Each window can also be programmed with a 197 * starting or base address relative to the PC card's address zero. 198 * Each window is a fixed 1Mb in size. 199 * 200 * Each window has two window control registers associated with it to 201 * control the window's PCMCIA bus timing parameters, PC card address 202 * space that the window maps, and the base address in the 203 * selected PC card's address space." 204 */ 205 #define STP4020_WINDOW_SIZE (1024*1024) /* 1MB */ 206 #define STP4020_WINDOW_SHIFT 20 /* for 1MB */ 207 208 /* 209 * PC card Window Control register 0 210 */ 211 #define STP4020_WCR0_rsvd 0x8000 /* reserved */ 212 #define STP4020_WCR0_CMDLNG_M 0x7c00 /* command strobe length bit mask */ 213 #define STP4020_WCR0_CMDLNG_S 10 /* command strobe length bit shift */ 214 #define STP4020_WCR0_CMDDLY_M 0x0300 /* command strobe delay bit mask */ 215 #define STP4020_WCR0_CMDDLY_S 8 /* command strobe delay bit shift */ 216 #define STP4020_MEM_SPEED_MIN 100 217 #define STP4020_MEM_SPEED_MAX 1370 218 /* 219 * The ASPSEL (Address Space Select) bits control which of the three PC card 220 * address spaces this window maps in. 221 */ 222 #define STP4020_WCR0_ASPSEL_M 0x00c0 /* address space select bit mask */ 223 #define STP4020_WCR0_ASPSEL_AM 0x0000 /* attribute memory */ 224 #define STP4020_WCR0_ASPSEL_CM 0x0040 /* common memory */ 225 #define STP4020_WCR0_ASPSEL_IO 0x0080 /* I/O */ 226 /* 227 * The base address controls which 1MB range in the 64MB card address space 228 * this window maps to. 229 */ 230 #define STP4020_WCR0_BASE_M 0x0003f /* base address bit mask */ 231 #define STP4020_WCR0_BASE_S 0 /* base address bit shift */ 232 233 #define STP4020_ADDR2PAGE(x) ((x) >> 20) 234 235 /* 236 * PC card Window Control register 1 237 */ 238 #define STP4020_WCR1_rsvd 0xffe0 /* reserved */ 239 #define STP4020_WCR1_RECDLY_M 0x0018 /* recovery delay bit mask */ 240 #define STP4020_WCR1_RECDLY_S 3 /* recovery delay bit shift */ 241 #define STP4020_WCR1_WAITDLY_M 0x0006 /* *WAIT signal delay bit mask */ 242 #define STP4020_WCR1_WAITDLY_S 1 /* *WAIT signal delay bit shift */ 243 #define STP4020_WCR1_WAITREQ_M 0x0001 /* *WAIT signal is required bit mask */ 244 #define STP4020_WCR1_WAITREQ_S 0 /* *WAIT signal is required bit shift */ 245 246 #if for_reference_only 247 /* 248 * STP4020 CSR structures 249 * 250 * There is one stp4020_regs_t structure per instance, and it refers to 251 * the complete Stp4020 register set. 252 * 253 * For each socket, there is one stp4020_socket_csr_t structure, which 254 * refers to all the registers for that socket. That structure is 255 * made up of the window register structures as well as the registers 256 * that control overall socket operation. 257 * 258 * For each window, there is one stp4020_window_ctl_t structure, which 259 * refers to all the registers for that window. 260 */ 261 262 /* 263 * per-window CSR structure 264 */ 265 typedef struct stp4020_window_ctl_t { 266 volatile ushort_t ctl0; /* window control register 0 */ 267 volatile ushort_t ctl1; /* window control register 1 */ 268 } stp4020_window_ctl_t; 269 270 /* 271 * per-socket CSR structure 272 */ 273 typedef struct stp4020_socket_csr_t { 274 volatile struct stp4020_window_ctl_t window[STP4020_NWIN]; 275 volatile ushort_t ctl0; /* socket control register 0 */ 276 volatile ushort_t ctl1; /* socket control register 1 */ 277 volatile ushort_t stat0; /* socket status register 0 */ 278 volatile ushort_t stat1; /* socket status register 1 */ 279 volatile uchar_t filler[12]; /* filler space */ 280 } stp4020_socket_csr_t; 281 282 /* 283 * per-instance CSR structure 284 */ 285 typedef struct stp4020_regs_t { 286 struct stp4020_socket_csr_t socket[STP4020_NSOCK]; /* socket CSRs */ 287 } stp4020_regs_t; 288 #endif /* reference */ 289 290 /* Size of control and status register banks */ 291 #define STP4020_SOCKREGS_SIZE 32 292 #define STP4020_WINREGS_SIZE 4 293 294 /* Relative socket control & status register offsets */ 295 #define STP4020_ICR0_IDX 12 296 #define STP4020_ICR1_IDX 14 297 #define STP4020_ISR0_IDX 16 298 #define STP4020_ISR1_IDX 18 299 300 /* Relative Window control register offsets */ 301 #define STP4020_WCR0_IDX 0 302 #define STP4020_WCR1_IDX 2 303 304 /* Socket control and status register offsets */ 305 #define STP4020_ICR0_REG(s) ((32 * (s)) + STP4020_ICR0_IDX) 306 #define STP4020_ICR1_REG(s) ((32 * (s)) + STP4020_ICR1_IDX) 307 #define STP4020_ISR0_REG(s) ((32 * (s)) + STP4020_ISR0_IDX) 308 #define STP4020_ISR1_REG(s) ((32 * (s)) + STP4020_ISR1_IDX) 309 310 /* Window control and status registers; one set per socket */ 311 #define STP4020_WCR0_REG(s,w) ((32 * (s)) + (4 * (w)) + STP4020_WCR0_IDX) 312 #define STP4020_WCR1_REG(s,w) ((32 * (s)) + (4 * (w)) + STP4020_WCR1_IDX) 313 314 #endif /* _STP4020_REG_H */ 315