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Searched refs:SVT (Results 1 – 24 of 24) sorted by relevance

/openbsd/gnu/llvm/llvm/include/llvm/MC/
H A DMCSymbolXCOFF.h51 void setVisibilityType(XCOFF::VisibilityType SVT) { VisibilityType = SVT; }; in setVisibilityType() argument
/openbsd/gnu/llvm/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp963 MVT SVT = VT.getSimpleVT(); in getTypeConversion() local
965 MVT NVT = TransformToType[SVT.SimpleTy]; in getTypeConversion()
1432 MVT SVT = (MVT::SimpleValueType) nVT; in computeRegisterProperties() local
1436 SVT.getVectorElementCount() == EC && isTypeLegal(SVT)) { in computeRegisterProperties()
1437 TransformToType[i] = SVT; in computeRegisterProperties()
1438 RegisterTypeForVT[i] = SVT; in computeRegisterProperties()
1454 MVT SVT = (MVT::SimpleValueType) nVT; in computeRegisterProperties() local
1455 if (SVT.getVectorElementType() == EltVT && in computeRegisterProperties()
1459 isTypeLegal(SVT)) { in computeRegisterProperties()
1460 TransformToType[i] = SVT; in computeRegisterProperties()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86InstCombineIntrinsic.cpp204 Type *SVT = VT->getElementType(); in simplifyX86immShift() local
207 unsigned BitWidth = SVT->getPrimitiveSizeInBits(); in simplifyX86immShift()
217 Amt = Builder.CreateZExtOrTrunc(Amt, SVT); in simplifyX86immShift()
226 Amt = ConstantInt::get(SVT, BitWidth - 1); in simplifyX86immShift()
233 cast<VectorType>(AmtVT)->getElementType() == SVT && in simplifyX86immShift()
260 cast<VectorType>(AmtVT)->getElementType() == SVT && in simplifyX86immShift()
352 Type *SVT = VT->getElementType(); in simplifyX86varShift() local
354 int BitWidth = SVT->getIntegerBitWidth(); in simplifyX86varShift()
406 ConstantVec.push_back(UndefValue::get(SVT)); in simplifyX86varShift()
423 ShiftVecAmts.push_back(UndefValue::get(SVT)); in simplifyX86varShift()
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H A DX86ISelLowering.cpp6820 DstVT = MVT::getVectorVT(SVT, 512 / SVT.getSizeInBits()); in getAVX512Node()
23385 if (SVT == MVT::f128 || (VT == MVT::f16 && SVT == MVT::f80)) in LowerFP_ROUND()
23388 if (VT == MVT::f16 && (SVT == MVT::f64 || SVT == MVT::f32) && in LowerFP_ROUND()
25882 if (SVT != MVT::i64 && SVT != MVT::i32 && SVT != MVT::i16) in LowerEXTEND_VECTOR_INREG()
45278 if (SVT != MVT::i64 && SVT != MVT::i32 && SVT != MVT::i16 && SVT != MVT::i8) in combineToExtendBoolVectorInReg()
50069 (SVT == MVT::i8 || SVT == MVT::i16) && in combineTruncateWithSat()
50096 (SVT == MVT::i32 || SVT == MVT::i16 || SVT == MVT::i8)) { in combineTruncateWithSat()
51575 if (SVT != MVT::i8 && SVT != MVT::i16 && SVT != MVT::i32) in combineVectorSignBitsTruncation()
52130 !(SVT == MVT::f32 || SVT == MVT::f64) || in getNegatedExpression()
52972 if (SVT != MVT::i8 && SVT != MVT::i16 && SVT != MVT::i32 && in combineExtSetcc()
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/openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp784 if (NVT.bitsGE(SVT)) in SoftenFloatRes_XINT_TO_FP()
795 CallOptions.setTypeListBeforeSoften(SVT, RVT, true); in SoftenFloatRes_XINT_TO_FP()
894 EVT SVT = Op.getValueType(); in SoftenFloatOp_FP_ROUND() local
969 EVT SVT = Op.getValueType(); in SoftenFloatOp_FP_TO_XINT() local
2788 EVT SVT = N->getOperand(0).getValueType(); in SoftPromoteHalfRes_FP_ROUND() local
2979 EVT SVT = Op.getValueType(); in SoftPromoteHalfOp_FP_EXTEND() local
2983 assert(SVT == MVT::f16); in SoftPromoteHalfOp_FP_EXTEND()
2998 EVT SVT = Op.getValueType(); in SoftPromoteHalfOp_FP_TO_XINT() local
3013 EVT SVT = Op.getValueType(); in SoftPromoteHalfOp_FP_TO_XINT_SAT() local
3033 EVT SVT = Op0.getValueType(); in SoftPromoteHalfOp_SELECT_CC() local
[all …]
H A DSelectionDAG.cpp2842 EVT LegalSVT = SVT; in getSplatValue()
2844 if (!SVT.isInteger()) in getSplatValue()
2847 if (LegalSVT.bitsLT(SVT)) in getSplatValue()
5110 EVT SVT = VT.getScalarType(); in foldCONCAT_VECTORS() local
5125 SVT = (SVT.bitsLT(Op.getValueType()) ? Op.getValueType() : SVT); in foldCONCAT_VECTORS()
5130 Op = DAG.getUNDEF(SVT); in foldCONCAT_VECTORS()
5974 if (LegalSVT != SVT) in FoldConstantArithmetic()
8205 if (VT == SVT) in getTruncStore()
8223 ID.AddInteger(SVT.getRawBits()); in getTruncStore()
8455 if (VT == SVT) in getTruncStoreVP()
[all …]
H A DLegalizeDAG.cpp308 EVT SVT = VT; in ExpandConstantFP() local
313 while (SVT != MVT::f32 && SVT != MVT::f16 && SVT != MVT::bf16) { in ExpandConstantFP()
314 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); in ExpandConstantFP()
318 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) && in ExpandConstantFP()
322 VT = SVT; in ExpandConstantFP()
3277 MVT SVT = Op.getSimpleValueType(); in ExpandNode() local
3278 if ((SVT == MVT::f64 || SVT == MVT::f80) && in ExpandNode()
4294 if (NVT.bitsGE(SVT)) in ConvertNodeToLibcall()
4323 EVT SVT = Op.getValueType(); in ConvertNodeToLibcall() local
4338 LC = Signed ? RTLIB::getFPTOSINT(SVT, NVT) in ConvertNodeToLibcall()
[all …]
H A DLegalizeIntegerTypes.cpp337 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType()); in PromoteIntRes_AtomicCmpSwap() local
342 if (!TLI.isTypeLegal(SVT)) in PromoteIntRes_AtomicCmpSwap()
343 SVT = NVT; in PromoteIntRes_AtomicCmpSwap()
654 EVT SVT = In.getValueType().getScalarType(); in PromoteIntRes_EXTRACT_VECTOR_ELT() local
655 if (SVT.bitsGE(NVT)) { in PromoteIntRes_EXTRACT_VECTOR_ELT()
837 EVT SVT = getSetCCResultType(VT); in PromoteIntRes_Overflow() local
1158 EVT SVT = getSetCCResultType(InVT); in PromoteIntRes_SETCC() local
1163 if (getTypeAction(SVT) == TargetLowering::TypePromoteInteger) { in PromoteIntRes_SETCC()
1166 SVT = getSetCCResultType(InVT); in PromoteIntRes_SETCC()
1169 SVT = NVT; in PromoteIntRes_SETCC()
[all …]
H A DTargetLowering.cpp5771 EVT SVT = VT.getScalarType(); in BuildExactSDIV() local
5861 EVT SVT = VT.getScalarType(); in BuildSDIV() local
6009 EVT SVT = VT.getScalarType(); in BuildUDIV() local
6082 dl, SVT); in BuildUDIV()
6250 EVT SVT = VT.getScalarType(); in prepareUREMEqFold() local
6340 PAmts.push_back(DAG.getConstant(P, DL, SVT)); in prepareUREMEqFold()
6343 QAmts.push_back(DAG.getConstant(Q, DL, SVT)); in prepareUREMEqFold()
6499 EVT SVT = VT.getScalarType(); in prepareSREMEqFold() local
6593 PAmts.push_back(DAG.getConstant(P, DL, SVT)); in prepareSREMEqFold()
6594 AAmts.push_back(DAG.getConstant(A, DL, SVT)); in prepareSREMEqFold()
[all …]
H A DDAGCombiner.cpp11828 EVT SVT = VT.getScalarType(); in tryToFoldExtendOfConstant() local
12331 if (SVT != N0.getValueType()) { in foldSextSetcc()
12344 if (SVT == MatchingVecType) { in foldSextSetcc()
13871 EVT SVT = VT.getScalarType(); in visitTRUNCATE() local
22336 EVT SVT = VT.getScalarType(); in visitCONCAT_VECTORS() local
22338 EVT MinVT = SVT; in visitCONCAT_VECTORS()
22339 if (!SVT.isFloatingPoint()) { in visitCONCAT_VECTORS()
23222 EVT SVT = VT.getScalarType(); in combineShuffleOfScalars() local
23223 if (SVT.isInteger()) in combineShuffleOfScalars()
23225 SVT = (SVT.bitsLT(Op.getValueType()) ? Op.getValueType() : SVT); in combineShuffleOfScalars()
[all …]
H A DLegalizeVectorTypes.cpp6446 EVT SVT = getSetCCResultType(InOp0.getValueType()); in WidenVecOp_SETCC() local
6449 SVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, in WidenVecOp_SETCC()
6450 SVT.getVectorElementCount()); in WidenVecOp_SETCC()
6453 SVT, InOp0, InOp1, N->getOperand(2)); in WidenVecOp_SETCC()
6457 SVT.getVectorElementType(), in WidenVecOp_SETCC()
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/
H A DValueTypes.h41 constexpr EVT(MVT::SimpleValueType SVT) : V(SVT) {} in EVT()
H A DSelectionDAG.h1398 MachinePointerInfo PtrInfo, EVT SVT, Align Alignment,
1403 MachinePointerInfo PtrInfo, EVT SVT,
1407 return getTruncStore(Chain, dl, Val, Ptr, PtrInfo, SVT,
1408 Alignment.value_or(getEVTAlign(SVT)), MMOFlags,
1415 MachinePointerInfo PtrInfo, EVT SVT, unsigned Alignment,
1418 return getTruncStore(Chain, dl, Val, Ptr, PtrInfo, SVT,
1422 SDValue Ptr, EVT SVT, MachineMemOperand *MMO);
1474 MachinePointerInfo PtrInfo, EVT SVT, Align Alignment,
1478 SDValue Ptr, SDValue Mask, SDValue EVL, EVT SVT,
1542 EVT SVT, Align Alignment,
[all …]
/openbsd/gnu/llvm/llvm/include/llvm/Support/
H A DMachineValueType.h344 constexpr MVT(SimpleValueType SVT) : SimpleTy(SVT) {} in MVT() argument
/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp1253 EVT SVT = (UW == 32 || UW == 64) ? MVT::getIntegerVT(UW) : UVT; in ppHoistZextI1() local
1254 SDValue Sel = DAG.getNode(ISD::SELECT, dl, SVT, OpI1, in ppHoistZextI1()
1255 DAG.getBitcast(SVT, If1), in ppHoistZextI1()
1256 DAG.getBitcast(SVT, If0)); in ppHoistZextI1()
H A DHexagonISelLowering.cpp3770 MVT SVT = VT.getSimpleVT(); in allowsMemoryAccess() local
3771 if (Subtarget.isHVXVectorType(SVT, true)) in allowsMemoryAccess()
3772 return allowsHvxMemoryAccess(SVT, Flags, Fast); in allowsMemoryAccess()
3780 MVT SVT = VT.getSimpleVT(); in allowsMisalignedMemoryAccesses() local
3781 if (Subtarget.isHVXVectorType(SVT, true)) in allowsMisalignedMemoryAccesses()
3782 return allowsHvxMisalignedMemoryAccesses(SVT, Flags, Fast); in allowsMisalignedMemoryAccesses()
H A DHexagonISelDAGToDAGHVX.cpp1178 MVT::SimpleValueType SVT = MVT::SimpleValueType(R.OpN & OpRef::Index); in materialize() local
1179 Ops.push_back(ISel.selectUndef(dl, MVT(SVT))); in materialize()
/openbsd/usr.bin/file/magdir/
H A Dsysex176 >>>4 byte 0x04 SVT (Velocity Curve)
/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp3189 MVT SVT = VT.getVectorElementType(); in lowerVECTOR_SHUFFLE() local
3207 Offset *= SVT.getStoreSize(); in lowerVECTOR_SHUFFLE()
3212 if (SVT.isInteger() && SVT.bitsGT(XLenVT)) { in lowerVECTOR_SHUFFLE()
3223 ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops, SVT, in lowerVECTOR_SHUFFLE()
3233 if (SVT.isFloatingPoint()) in lowerVECTOR_SHUFFLE()
3234 V = DAG.getLoad(SVT, DL, Ld->getChain(), NewAddr, in lowerVECTOR_SHUFFLE()
3528 MVT SVT = VT.getSimpleVT(); in isShuffleMaskLegal() local
3533 isInterleaveShuffle(M, SVT, SwapSources, Subtarget); in isShuffleMaskLegal()
13977 EVT SVT = VT.getScalarType(); in isFMAFasterThanFMulAndFAdd() local
13979 if (!SVT.isSimple()) in isFMAFasterThanFMulAndFAdd()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp6820 static const TargetRegisterClass *getRegClassForSVT(MVT::SimpleValueType SVT, in getRegClassForSVT() argument
6824 assert((IsPPC64 || SVT != MVT::i64) && in getRegClassForSVT()
6827 switch (SVT) { in getRegClassForSVT()
7011 MVT::SimpleValueType SVT = VA.getLocVT().SimpleTy; in LowerFormalArguments_AIX() local
7013 getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(), in LowerFormalArguments_AIX()
7152 MVT::SimpleValueType SVT = ValVT.SimpleTy; in LowerFormalArguments_AIX() local
7155 getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(), in LowerFormalArguments_AIX()
11418 EVT SVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), in ReplaceNodeResults() local
11420 SDVTList VTs = DAG.getVTList(SVT, MVT::Other); in ReplaceNodeResults()
/openbsd/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp419 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; in allowsMisalignedMemoryAccesses() local
431 switch (SVT) { in allowsMisalignedMemoryAccesses()
/openbsd/gnu/llvm/llvm/utils/TableGen/
H A DGlobalISelEmitter.cpp203 static std::optional<LLTCodeGen> MVTToLLT(MVT::SimpleValueType SVT) { in MVTToLLT() argument
204 MVT VT(SVT); in MVTToLLT()
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp11831 MVT SVT = Node->getValueType(0).getVectorElementType().getSimpleVT(); in adjustWritemask() local
11834 SVT : MVT::getVectorVT(SVT, NewChannels == 3 ? 4 : in adjustWritemask()
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp8725 EVT SVT = VT.getScalarType() == MVT::i8 || VT.getScalarType() == MVT::i16 in LowerVECTOR_SHUFFLEUsingOneOff() local
8729 ISD::EXTRACT_VECTOR_ELT, dl, SVT, in LowerVECTOR_SHUFFLEUsingOneOff()
20445 const SDNode *N, MVT::SimpleValueType SVT) { in getDivRemLibcall() argument
20452 switch (SVT) { in getDivRemLibcall()