1 /* $OpenBSD: octiic.c,v 1.3 2020/09/10 16:40:40 visa Exp $ */
2
3 /*
4 * Copyright (c) 2019 Visa Hankala
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 /*
20 * Driver for OCTEON two-wire serial interface core.
21 */
22
23 #include <sys/param.h>
24 #include <sys/systm.h>
25 #include <sys/device.h>
26 #include <sys/stdint.h>
27
28 #include <machine/bus.h>
29 #include <machine/fdt.h>
30 #include <machine/octeonvar.h>
31
32 #define _I2C_PRIVATE
33 #include <dev/i2c/i2cvar.h>
34
35 #include <dev/ofw/fdt.h>
36 #include <dev/ofw/openfirm.h>
37 #include <dev/ofw/ofw_misc.h>
38
39 struct octiic_softc {
40 struct device sc_dev;
41 int sc_node;
42 bus_space_tag_t sc_iot;
43 bus_space_handle_t sc_ioh;
44
45 struct i2c_bus sc_i2c_bus;
46 struct i2c_controller sc_i2c_tag;
47 struct rwlock sc_i2c_lock;
48
49 int sc_start_sent;
50 };
51
52 int octiic_match(struct device *, void *, void *);
53 void octiic_attach(struct device *, struct device *, void *);
54
55 int octiic_i2c_acquire_bus(void *, int);
56 void octiic_i2c_release_bus(void *, int);
57 int octiic_i2c_send_start(void *, int);
58 int octiic_i2c_send_stop(void *, int);
59 int octiic_i2c_initiate_xfer(void *, i2c_addr_t, int);
60 int octiic_i2c_read_byte(void *, uint8_t *, int);
61 int octiic_i2c_write_byte(void *, uint8_t, int);
62 void octiic_i2c_scan(struct device *, struct i2cbus_attach_args *, void *);
63
64 int octiic_reg_read(struct octiic_softc *, uint8_t, uint8_t *);
65 int octiic_reg_write(struct octiic_softc *, uint8_t, uint8_t);
66 int octiic_set_clock(struct octiic_softc *, uint32_t);
67 int octiic_wait(struct octiic_softc *, uint8_t, int);
68
69 const struct cfattach octiic_ca = {
70 sizeof(struct octiic_softc), octiic_match, octiic_attach
71 };
72
73 struct cfdriver octiic_cd = {
74 NULL, "octiic", DV_DULL
75 };
76
77 #define TWSI_RD_8(sc, reg) \
78 bus_space_read_8((sc)->sc_iot, (sc)->sc_ioh, (reg))
79 #define TWSI_WR_8(sc, reg, val) \
80 bus_space_write_8((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
81
82 #define TWSI_SW_TWSI 0x00
83 #define TWSI_SW_TWSI_V 0x8000000000000000ull
84 #define TWSI_SW_TWSI_SLONLY 0x4000000000000000ull
85 #define TWSI_SW_TWSI_EIA 0x2000000000000000ull
86 #define TWSI_SW_TWSI_OP_M 0x1e00000000000000ull
87 #define TWSI_SW_TWSI_OP_S 57
88 #define TWSI_SW_TWSI_R 0x0100000000000000ull
89 #define TWSI_SW_TWSI_SOVR 0x0080000000000000ull
90 #define TWSI_SW_TWSI_SIZE_M 0x0070000000000000ull
91 #define TWSI_SW_TWSI_SIZE_S 52
92 #define TWSI_SW_TWSI_SCR_M 0x000c000000000000ull
93 #define TWSI_SW_TWSI_SCR_S 50
94 #define TWSI_SW_TWSI_A_M 0x0003ff0000000000ull
95 #define TWSI_SW_TWSI_A_S 40
96 #define TWSI_SW_TWSI_IA_M 0x000000f800000000ull
97 #define TWSI_SW_TWSI_IA_S 35
98 #define TWSI_SW_TWSI_EOP_IA_M 0x0000000700000000ull
99 #define TWSI_SW_TWSI_EOP_IA_S 32
100 #define TWSI_SW_TWSI_D_M 0x00000000ffffffffull
101
102 /* Opcodes for field TWSI_SW_TWSI_OP */
103 #define TWSI_OP_CLK 0x04
104 #define TWSI_OP_EOP 0x06
105
106 /* Addresses for field TWSI_SW_TWSI_IA */
107 #define TWSI_IA_DATA 0x01
108 #define TWSI_IA_CTL 0x02
109 #define TWSI_IA_CLKCTL 0x03 /* write only */
110 #define TWSI_IA_STAT 0x03 /* read only */
111 #define TWSI_IA_RST 0x07
112
113 #define TWSI_INT 0x10
114
115 /* Control register bits */
116 #define TWSI_CTL_CE 0x80
117 #define TWSI_CTL_ENAB 0x40
118 #define TWSI_CTL_STA 0x20
119 #define TWSI_CTL_STP 0x10
120 #define TWSI_CTL_IFLG 0x08
121 #define TWSI_CTL_AAK 0x04
122
123 /* Core states */
124 #define TWSI_STAT_ERROR 0x00
125 #define TWSI_STAT_START 0x08
126 #define TWSI_STAT_RSTART 0x10
127 #define TWSI_STAT_AWT_ACK 0x18
128 #define TWSI_STAT_MBT_ACK 0x28
129 #define TWSI_STAT_ART_ACK 0x40
130 #define TWSI_STAT_MBR_ACK 0x50
131 #define TWSI_STAT_MBR_NAK 0x58
132 #define TWSI_STAT_IDLE 0xf8
133
134 int
octiic_match(struct device * parent,void * match,void * aux)135 octiic_match(struct device *parent, void *match, void *aux)
136 {
137 struct fdt_attach_args *fa = aux;
138
139 return OF_is_compatible(fa->fa_node, "cavium,octeon-3860-twsi") ||
140 OF_is_compatible(fa->fa_node, "cavium,octeon-7890-twsi");
141 }
142
143 void
octiic_attach(struct device * parent,struct device * self,void * aux)144 octiic_attach(struct device *parent, struct device *self, void *aux)
145 {
146 struct i2cbus_attach_args iba;
147 struct fdt_attach_args *faa = aux;
148 struct octiic_softc *sc = (struct octiic_softc *)self;
149 uint32_t freq;
150
151 sc->sc_node = faa->fa_node;
152 sc->sc_iot = faa->fa_iot;
153
154 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, faa->fa_reg[0].size,
155 0, &sc->sc_ioh)) {
156 printf(": failed to map registers\n");
157 return;
158 }
159
160 freq = OF_getpropint(faa->fa_node, "clock-frequency", 100000);
161 if (octiic_set_clock(sc, freq) != 0) {
162 printf(": clock setup failed\n");
163 return;
164 }
165
166 /* Reset the controller. */
167 if (octiic_reg_write(sc, TWSI_IA_RST, 0) != 0) {
168 printf(": register write timeout\n");
169 return;
170 }
171
172 delay(1000);
173
174 if (octiic_wait(sc, TWSI_STAT_IDLE, I2C_F_POLL) != 0) {
175 printf(": reset failed\n");
176 return;
177 }
178
179 printf("\n");
180
181 rw_init(&sc->sc_i2c_lock, "iiclk");
182 sc->sc_i2c_tag.ic_cookie = sc;
183 sc->sc_i2c_tag.ic_acquire_bus = octiic_i2c_acquire_bus;
184 sc->sc_i2c_tag.ic_release_bus = octiic_i2c_release_bus;
185 sc->sc_i2c_tag.ic_send_start = octiic_i2c_send_start;
186 sc->sc_i2c_tag.ic_send_stop = octiic_i2c_send_stop;
187 sc->sc_i2c_tag.ic_initiate_xfer = octiic_i2c_initiate_xfer;
188 sc->sc_i2c_tag.ic_read_byte = octiic_i2c_read_byte;
189 sc->sc_i2c_tag.ic_write_byte = octiic_i2c_write_byte;
190
191 memset(&iba, 0, sizeof(iba));
192 iba.iba_name = "iic";
193 iba.iba_tag = &sc->sc_i2c_tag;
194 iba.iba_bus_scan = octiic_i2c_scan;
195 iba.iba_bus_scan_arg = sc;
196 config_found(self, &iba, iicbus_print);
197
198 sc->sc_i2c_bus.ib_node = sc->sc_node;
199 sc->sc_i2c_bus.ib_ic = &sc->sc_i2c_tag;
200 i2c_register(&sc->sc_i2c_bus);
201 }
202
203 int
octiic_i2c_acquire_bus(void * arg,int flags)204 octiic_i2c_acquire_bus(void *arg, int flags)
205 {
206 struct octiic_softc *sc = arg;
207
208 if (cold || (flags & I2C_F_POLL))
209 return 0;
210
211 return rw_enter(&sc->sc_i2c_lock, RW_WRITE | RW_INTR);
212 }
213
214 void
octiic_i2c_release_bus(void * arg,int flags)215 octiic_i2c_release_bus(void *arg, int flags)
216 {
217 struct octiic_softc *sc = arg;
218
219 if (cold || (flags & I2C_F_POLL))
220 return;
221
222 rw_exit(&sc->sc_i2c_lock);
223 }
224
225 int
octiic_i2c_send_start(void * cookie,int flags)226 octiic_i2c_send_start(void *cookie, int flags)
227 {
228 struct octiic_softc *sc = cookie;
229 int error;
230 uint8_t nstate;
231
232 error = octiic_reg_write(sc, TWSI_IA_CTL, TWSI_CTL_ENAB | TWSI_CTL_STA);
233 if (error != 0)
234 return error;
235
236 delay(10);
237
238 if (sc->sc_start_sent)
239 nstate = TWSI_STAT_RSTART;
240 else
241 nstate = TWSI_STAT_START;
242 error = octiic_wait(sc, nstate, flags);
243 if (error != 0)
244 return error;
245
246 sc->sc_start_sent = 1;
247
248 return 0;
249 }
250
251 int
octiic_i2c_send_stop(void * cookie,int flags)252 octiic_i2c_send_stop(void *cookie, int flags)
253 {
254 struct octiic_softc *sc = cookie;
255
256 sc->sc_start_sent = 0;
257
258 return octiic_reg_write(sc, TWSI_IA_CTL, TWSI_CTL_ENAB | TWSI_CTL_STP);
259 }
260
261 int
octiic_i2c_initiate_xfer(void * cookie,i2c_addr_t addr,int flags)262 octiic_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags)
263 {
264 struct octiic_softc *sc = cookie;
265 int error;
266 uint8_t mode = 0, nstate;
267
268 error = octiic_i2c_send_start(sc, flags);
269 if (error != 0)
270 return error;
271
272 if (flags & I2C_F_READ)
273 mode = 0x01;
274 nstate = flags & I2C_F_READ ? TWSI_STAT_ART_ACK : TWSI_STAT_AWT_ACK;
275
276 /* Handle 10-bit addressing. */
277 if (addr > 0x7f) {
278 octiic_reg_write(sc, TWSI_IA_DATA, ((addr >> 7) << 1) | mode);
279 octiic_reg_write(sc, TWSI_IA_CTL, TWSI_CTL_ENAB);
280
281 error = octiic_wait(sc, nstate, flags);
282 if (error != 0)
283 return error;
284 }
285
286 octiic_reg_write(sc, TWSI_IA_DATA, ((addr & 0x7f) << 1) | mode);
287 octiic_reg_write(sc, TWSI_IA_CTL, TWSI_CTL_ENAB);
288
289 error = octiic_wait(sc, nstate, flags);
290 if (error != 0)
291 return error;
292
293 return 0;
294 }
295
296 int
octiic_i2c_read_byte(void * cookie,uint8_t * datap,int flags)297 octiic_i2c_read_byte(void *cookie, uint8_t *datap, int flags)
298 {
299 struct octiic_softc *sc = cookie;
300 int error;
301 uint8_t ctl, nstate;
302
303 ctl = TWSI_CTL_ENAB;
304 if ((flags & I2C_F_LAST) == 0)
305 ctl |= TWSI_CTL_AAK;
306 octiic_reg_write(sc, TWSI_IA_CTL, ctl);
307
308 nstate = flags & I2C_F_LAST ? TWSI_STAT_MBR_NAK : TWSI_STAT_MBR_ACK;
309 error = octiic_wait(sc, nstate, flags);
310 if (error != 0)
311 return error;
312
313 octiic_reg_read(sc, TWSI_IA_DATA, datap);
314
315 if (flags & I2C_F_STOP)
316 error = octiic_i2c_send_stop(sc, flags);
317
318 return 0;
319 }
320
321 int
octiic_i2c_write_byte(void * cookie,uint8_t data,int flags)322 octiic_i2c_write_byte(void *cookie, uint8_t data, int flags)
323 {
324 struct octiic_softc *sc = cookie;
325 int error;
326
327 octiic_reg_write(sc, TWSI_IA_DATA, data);
328 octiic_reg_write(sc, TWSI_IA_CTL, TWSI_CTL_ENAB);
329
330 error = octiic_wait(sc, TWSI_STAT_MBT_ACK, flags);
331 if (error != 0)
332 return error;
333
334 if (flags & I2C_F_STOP)
335 error = octiic_i2c_send_stop(sc, flags);
336
337 return error;
338 }
339
340 void
octiic_i2c_scan(struct device * self,struct i2cbus_attach_args * iba,void * arg)341 octiic_i2c_scan(struct device *self, struct i2cbus_attach_args *iba, void *arg)
342 {
343 struct i2c_attach_args ia;
344 char name[32];
345 uint32_t reg[1];
346 struct octiic_softc *sc = arg;
347 int node;
348
349 for (node = OF_child(sc->sc_node); node != 0; node = OF_peer(node)) {
350 memset(name, 0, sizeof(name));
351 memset(reg, 0, sizeof(reg));
352
353 if (OF_getprop(node, "compatible", name, sizeof(name)) == -1)
354 continue;
355 if (name[0] == '\0')
356 continue;
357
358 if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
359 continue;
360
361 memset(&ia, 0, sizeof(ia));
362 ia.ia_tag = iba->iba_tag;
363 ia.ia_addr = reg[0];
364 ia.ia_name = name;
365 ia.ia_cookie = &node;
366 config_found(self, &ia, iic_print);
367 }
368 }
369
370 int
octiic_reg_read(struct octiic_softc * sc,uint8_t reg,uint8_t * pval)371 octiic_reg_read(struct octiic_softc *sc, uint8_t reg, uint8_t *pval)
372 {
373 uint64_t data;
374 int timeout;
375
376 TWSI_WR_8(sc, TWSI_SW_TWSI, TWSI_SW_TWSI_V | TWSI_SW_TWSI_R |
377 ((uint64_t)TWSI_OP_EOP << TWSI_SW_TWSI_OP_S) |
378 ((uint64_t)reg << TWSI_SW_TWSI_EOP_IA_S));
379
380 for (timeout = 100000; timeout > 0; timeout--) {
381 data = TWSI_RD_8(sc, TWSI_SW_TWSI);
382 if ((data & TWSI_SW_TWSI_V) == 0)
383 break;
384 delay(1);
385 }
386 if (timeout == 0)
387 return ETIMEDOUT;
388
389 *pval = (uint8_t)data;
390 return 0;
391 }
392
393 int
octiic_reg_write(struct octiic_softc * sc,uint8_t reg,uint8_t val)394 octiic_reg_write(struct octiic_softc *sc, uint8_t reg, uint8_t val)
395 {
396 uint64_t data;
397 int timeout;
398
399 TWSI_WR_8(sc, TWSI_SW_TWSI, TWSI_SW_TWSI_V |
400 ((uint64_t)TWSI_OP_EOP << TWSI_SW_TWSI_OP_S) |
401 ((uint64_t)reg << TWSI_SW_TWSI_EOP_IA_S) | val);
402
403 for (timeout = 100000; timeout > 0; timeout--) {
404 data = TWSI_RD_8(sc, TWSI_SW_TWSI);
405 if ((data & TWSI_SW_TWSI_V) == 0)
406 break;
407 delay(1);
408 }
409 if (timeout == 0)
410 return ETIMEDOUT;
411
412 return 0;
413 }
414
415 /*
416 * Wait until the controller has finished current operation.
417 * Fail if the new state is not `nstate'.
418 */
419 int
octiic_wait(struct octiic_softc * sc,uint8_t nstate,int flags)420 octiic_wait(struct octiic_softc *sc, uint8_t nstate, int flags)
421 {
422 uint8_t ctl, stat;
423 int timeout;
424
425 for (timeout = 100000; timeout > 0; timeout--) {
426 octiic_reg_read(sc, TWSI_IA_CTL, &ctl);
427 if (ctl & TWSI_CTL_IFLG)
428 break;
429 }
430
431 octiic_reg_read(sc, TWSI_IA_STAT, &stat);
432 if (stat != nstate)
433 return EIO;
434
435 return 0;
436 }
437
438 int
octiic_set_clock(struct octiic_softc * sc,uint32_t freq)439 octiic_set_clock(struct octiic_softc *sc, uint32_t freq)
440 {
441 uint64_t best_tclk = 0, tclk;
442 uint64_t ioclk = octeon_ioclock_speed();
443 int best_m = 2, best_n = 0, best_thp = 24;
444 int m, n, thp;
445
446 /*
447 * Find a combination of clock dividers `thp', `m' and `n' that gives
448 * bus frequency close to but no more than `freq'.
449 */
450 #define TCLK(ioclk, thp, n, m) \
451 ((ioclk) / (20 * ((thp) + 1) * (1 << (n)) * ((m) + 1)))
452 for (thp = 6; thp <= 72 && best_tclk < freq; thp <<= 1) {
453 for (n = 7; n > 0; n--) {
454 if (TCLK(ioclk, thp, n, 16) > freq)
455 break;
456 }
457 for (m = 15; m > 2; m--) {
458 if (TCLK(ioclk, thp, n, m - 1) > freq)
459 break;
460 }
461
462 tclk = TCLK(ioclk, thp, n, m);
463 if (tclk <= freq && tclk > best_tclk) {
464 best_tclk = tclk;
465 best_thp = thp;
466 best_m = m;
467 best_n = n;
468 }
469 }
470 #undef TCLK
471
472 TWSI_WR_8(sc, TWSI_SW_TWSI, TWSI_SW_TWSI_V |
473 ((uint64_t)TWSI_OP_CLK << TWSI_SW_TWSI_OP_S) | best_thp);
474
475 octiic_reg_write(sc, TWSI_IA_CLKCTL, (best_m << 3) | best_n);
476
477 return 0;
478 }
479