| /openbsd/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | IntrinsicLowering.cpp | 71 Value *Tmp4 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 24), in LowerBSWAP() local
85 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or1"); in LowerBSWAP()
87 V = Builder.CreateOr(Tmp4, Tmp2, "bswap.i32"); in LowerBSWAP()
99 Value* Tmp4 = Builder.CreateLShr(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
122 Tmp4 = Builder.CreateAnd(Tmp4, in LowerBSWAP()
136 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or3"); in LowerBSWAP()
139 Tmp4 = Builder.CreateOr(Tmp4, Tmp2, "bswap.or6"); in LowerBSWAP()
140 V = Builder.CreateOr(Tmp8, Tmp4, "bswap.i64"); in LowerBSWAP()
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| /openbsd/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 3886 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchBEXTRFromAndImm() local
3922 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPISTR() local
3955 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPESTR() local
4248 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchVPTERNLOG() local
4252 Tmp4)) { in matchVPTERNLOG()
4263 Tmp4)) { in matchVPTERNLOG()
4634 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in tryVPTESTM() local
5134 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
5187 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
5269 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
[all …]
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| /openbsd/gnu/llvm/llvm/lib/Transforms/Utils/ |
| H A D | IntegerDivision.cpp | 129 Value *Tmp4 = Builder.CreateXor(Q_Mag, Q_Sgn); in generateSignedDivisionCode() local
130 Value *Q = Builder.CreateSub(Tmp4, Q_Sgn); in generateSignedDivisionCode()
263 Value *Tmp4 = Builder.CreateAdd(Divisor, NegOne); in generateUnsignedDivisionCode() local
294 Value *Tmp9 = Builder.CreateSub(Tmp4, Tmp7); in generateUnsignedDivisionCode()
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| /openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 2692 SDValue Tmp1, Tmp2, Tmp3, Tmp4; in ExpandNode() local
3722 Tmp4 = Node->getOperand(3); // False in ExpandNode()
3775 std::swap(Tmp3, Tmp4); in ExpandNode()
3786 Tmp2, Tmp3, Tmp4, CC); in ExpandNode()
3799 Tmp4 = Node->getOperand(1); // CC in ExpandNode()
3809 if (Tmp4.getNode()) { in ExpandNode()
4501 SDValue Tmp1, Tmp2, Tmp3, Tmp4; in PromoteNode() local
4837 {Tmp4, Tmp1, Tmp2, Tmp3}); in PromoteNode()
4839 {Tmp4.getValue(1), Tmp4, DAG.getIntPtrConstant(0, dl)}); in PromoteNode()
4840 Results.push_back(Tmp4); in PromoteNode()
[all …]
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| H A D | TargetLowering.cpp | 8327 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5; in expandVPCTPOP() local
8633 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); in expandBSWAP()
8635 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); in expandBSWAP()
8648 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, in expandBSWAP()
8659 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); in expandBSWAP()
8662 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); in expandBSWAP()
8663 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); in expandBSWAP()
8701 Tmp4 = DAG.getNode(ISD::VP_OR, dl, VT, Tmp4, Tmp3, Mask, EVL); in expandVPBSWAP()
8721 Tmp4 = DAG.getNode(ISD::VP_AND, dl, VT, Tmp4, in expandVPBSWAP()
8735 Tmp4 = DAG.getNode(ISD::VP_OR, dl, VT, Tmp4, Tmp3, Mask, EVL); in expandVPBSWAP()
[all …]
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| /openbsd/gnu/llvm/clang/lib/CodeGen/ |
| H A D | CGExprComplex.cpp | 917 llvm::Value *Tmp4 = Builder.CreateMul(RHSr, RHSr); // c*c in EmitBinDiv() local
919 llvm::Value *Tmp6 = Builder.CreateAdd(Tmp4, Tmp5); // cc+dd in EmitBinDiv()
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| /openbsd/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 2470 SDValue Tmp4 = DAG.getNode(ShRight, dl, IntTy, {Tmp2, One}); in emitHvxShiftRightRnd() local
2472 SDValue Mux = DAG.getNode(ISD::VSELECT, dl, IntTy, {Eq, Tmp5, Tmp4}); in emitHvxShiftRightRnd()
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| /openbsd/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 8851 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); in LowerSHL_PARTS() local
8855 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); in LowerSHL_PARTS()
8880 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRL_PARTS() local
8884 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); in LowerSRL_PARTS()
8908 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRA_PARTS() local
8914 Tmp4, Tmp6, ISD::SETLE); in LowerSRA_PARTS()
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