1 /* $OpenBSD: ufshcireg.h,v 1.14 2024/06/15 18:26:25 mglocker Exp $ */ 2 3 /* 4 * Copyright (c) 2022 Marcus Glocker <mglocker@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Generic parameters. 21 */ 22 #define UFSHCI_UCD_PRDT_MAX_SEGS 64 23 #define UFSHCI_UCD_PRDT_MAX_XFER (UFSHCI_UCD_PRDT_MAX_SEGS * PAGE_SIZE) 24 #define UFSHCI_INTR_AGGR_TIMEOUT 0x08 /* 320us (1 unit = 40us) */ 25 #define UFSHCI_INTR_AGGR_COUNT_MAX 31 26 #define UFSHCI_SLOTS_MIN 1 27 #define UFSHCI_SLOTS_MAX 32 28 #define UFSHCI_TARGETS_MAX 1 29 #define UFSHCI_LBS 4096 /* UFS Logical Block Size: 30 For UFS minimum size shall be 31 4096 bytes */ 32 33 /* 34 * Controller Capabilities Registers 35 */ 36 37 /* Controller Capabilities */ 38 #define UFSHCI_REG_CAP 0x00 39 #define UFSHCI_REG_CAP_CS (1 << 28) /* RO */ 40 #define UFSHCI_REG_CAP_UICDMETMS (1 << 26) /* RO */ 41 #define UFSHCI_REG_CAP_OODDS (1 << 25) /* RO */ 42 #define UFSHCI_REG_CAP_64AS (1 << 24) /* RO */ 43 #define UFSHCI_REG_AUTOH8 (1 << 23) /* RO */ 44 #define UFSHCI_REG_CAP_NUTMRS(x) ((x >> 16) & 0x00000007) /* RO */ 45 #define UFSHCI_REG_CAP_RTT(x) ((x >> 8) & 0x000000ff) /* RO */ 46 #define UFSHCI_REG_CAP_NUTRS(x) ((x >> 0) & 0x0000001f) /* RO */ 47 /* UFS Version in BCD format */ 48 #define UFSHCI_REG_VER 0x08 49 #define UFSHCI_REG_VER_MAJOR(x) ((x >> 8) & 0x0000000f) /* RO */ 50 #define UFSHCI_REG_VER_MINOR(x) ((x >> 4) & 0x0000000f) /* RO */ 51 #define UFSHCI_REG_VER_SUFFIX(x) ((x >> 0) & 0x0000000f) /* RO */ 52 /* Product ID */ 53 #define UFSHCI_REG_HCPID 0x10 54 /* Manufacturer ID */ 55 #define UFSHCI_REG_HCMID 0x14 56 #define UFSHCI_REG_HCMID_BI(x) ((x >> 8) & 0x000000ff) /* RO */ 57 #define UFSHCI_REG_HCMID_MIC(x) ((x >> 0) & 0x000000ff) /* RO */ 58 /* Auto-Hibernate Idle Timer */ 59 #define UFSHCI_REG_AHIT 0x18 60 #define UFSHCI_REG_AHIT_TS(x) (x << 10) 61 #define UFSHCI_REG_AHIT_TS_1US 0x00 62 #define UFSHCI_REG_AHIT_TS_10US 0x01 63 #define UFSHCI_REG_AHIT_TS_100US 0x02 64 #define UFSHCI_REG_AHIT_TS_1MS 0x03 65 #define UFSHCI_REG_AHIT_TS_10MS 0x04 66 #define UFSHCI_REG_AHIT_TS_100MS 0x05 67 68 /* 69 * Operation and Runtime Registers 70 */ 71 72 /* Interrupt Status */ 73 #define UFSHCI_REG_IS 0x20 74 #define UFSHCI_REG_IS_CEFES (1 << 18) /* RWC */ 75 #define UFSHCI_REG_IS_SBFES (1 << 17) /* RWC */ 76 #define UFSHCI_REG_IS_HCFES (1 << 16) /* RWC */ 77 #define UFSHCI_REG_IS_UTPES (1 << 12) /* RWC */ 78 #define UFSHCI_REG_IS_DFES (1 << 11) /* RWC */ 79 #define UFSHCI_REG_IS_UCCS (1 << 10) /* RWC */ 80 #define UFSHCI_REG_IS_UTMRCS (1 << 9) /* RWC */ 81 #define UFSHCI_REG_IS_ULSS (1 << 8) /* RWC */ 82 #define UFSHCI_REG_IS_ULLS (1 << 7) /* RWC */ 83 #define UFSHCI_REG_IS_UHES (1 << 6) /* RWC */ 84 #define UFSHCI_REG_IS_UHXS (1 << 5) /* RWC */ 85 #define UFSHCI_REG_IS_UPMS (1 << 4) /* RWC */ 86 #define UFSHCI_REG_IS_UTMS (1 << 3) /* RWC */ 87 #define UFSHCI_REG_IS_UE (1 << 2) /* RWC */ 88 #define UFSHCI_REG_IS_UDEPRI (1 << 1) /* RWC */ 89 #define UFSHCI_REG_IS_UTRCS (1 << 0) /* RWC */ 90 /* Interrupt Enable */ 91 #define UFSHCI_REG_IE 0x24 92 #define UFSHCI_REG_IE_CEFFE (1 << 18) /* RW */ 93 #define UFSHCI_REG_IE_SBFEE (1 << 17) /* RW */ 94 #define UFSHCI_REG_IE_HCFEE (1 << 16) /* RW */ 95 #define UFSHCI_REG_IE_UTPEE (1 << 12) /* RW */ 96 #define UFSHCI_REG_IE_DFEE (1 << 11) /* RW */ 97 #define UFSHCI_REG_IE_UCCE (1 << 10) /* RW */ 98 #define UFSHCI_REG_IE_UTMRCE (1 << 9) /* RW */ 99 #define UFSHCI_REG_IE_ULSSE (1 << 8) /* RW */ 100 #define UFSHCI_REG_IE_ULLSE (1 << 7) /* RW */ 101 #define UFSHCI_REG_IE_UHESE (1 << 6) /* RW */ 102 #define UFSHCI_REG_IE_UHXSE (1 << 5) /* RW */ 103 #define UFSHCI_REG_IE_UPMSE (1 << 4) /* RW */ 104 #define UFSHCI_REG_IE_UTMSE (1 << 3) /* RW */ 105 #define UFSHCI_REG_IE_UEE (1 << 2) /* RW */ 106 #define UFSHCI_REG_IE_UDEPRIE (1 << 1) /* RW */ 107 #define UFSHCI_REG_IE_UTRCE (1 << 0) /* RW */ 108 /* Host Controller Status */ 109 #define UFSHCI_REG_HCS 0x30 110 #define UFSHCI_REG_HCS_TLUNUTPE(x) ((x >> 24) & 0x000000ff) /* RO */ 111 #define UFSHCI_REG_HCS_TTAGUTPE(x) ((x >> 16) & 0x000000ff) /* RO */ 112 #define UFSHCI_REG_HCS_UTPEC(x) ((x >> 12) & 0x0000000f) /* RO */ 113 #define UFSHCI_REG_HCS_UPMCRS(x) ((x >> 8) & 0x00000007) /* RO */ 114 #define UFSHCI_REG_HCS_UPMCRS_PWR_OK 0x00 115 #define UFSHCI_REG_HCS_UPMCRS_PWR_LOCAL 0x01 116 #define UFSHCI_REG_HCS_UPMCRS_PWR_REMTOTE 0x02 117 #define UFSHCI_REG_HCS_UMPCRS_PWR_BUSY 0x03 118 #define UFSHCI_REG_HCS_UMPCRS_PWR_ERROR_CAP 0x04 119 #define UFSHCI_REG_HCS_UMPCRS_PWR_FATAL_ERROR 0x05 120 #define UFSHCI_REG_HCS_UCRDY (1 << 3) /* RO */ 121 #define UFSHCI_REG_HCS_UTMRLRDY (1 << 2) /* RO */ 122 #define UFSHCI_REG_HCS_UTRLRDY (1 << 1) /* RO */ 123 #define UFSHCI_REG_HCS_DP (1 << 0) /* RO */ 124 /* Host Controller Enable */ 125 #define UFSHCI_REG_HCE 0x34 126 #define UFSHCI_REG_HCE_CGE (1 << 1) /* RW */ 127 #define UFSHCI_REG_HCE_HCE (1 << 0) /* RW */ 128 /* Host UIC Error Code PHY Adapter Layer */ 129 #define UFSHCI_REG_UECPA 0x38 130 /* Host UIC Error Code Data Link Layer */ 131 #define UFSHCI_REG_UECDL 0x3C 132 /* Host UIC Error Code Network Layer */ 133 #define UFSHCI_REG_UECN 0x40 134 /* Host UIC Error Code Transport Layer */ 135 #define UFSHCI_REG_UECT 0x44 136 /* Host UIC Error Code */ 137 #define UFSHCI_REG_UECDME 0x48 138 /* UTP Transfer Request Interrupt Aggregation Control Register */ 139 #define UFSHCI_REG_UTRIACR 0x4C 140 #define UFSHCI_REG_UTRIACR_IAEN (1U << 31) /* RW */ 141 #define UFSHCI_REG_UTRIACR_IAPWEN (1 << 24) /* WO */ 142 #define UFSHCI_REG_UTRIACR_IASB (1 << 20) /* RO */ 143 #define UFSHCI_REG_UTRIACR_CTR (1 << 16) /* WO */ 144 #define UFSHCI_REG_UTRIACR_IACTH(x) (x << 8) /* RW, max. val = 31 */ 145 #define UFSHCI_REG_UTRIACR_IATOVAL(x) (x << 0) /* RW, 40us units (1=40us) */ 146 147 /* 148 * UTP Transfer Request List Registers 149 */ 150 151 /* Base Address */ 152 #define UFSHCI_REG_UTRLBA 0x50 /* RW */ 153 /* Base Address Upper 32-bits */ 154 #define UFSHCI_REG_UTRLBAU 0x54 /* RW */ 155 /* Door Bell Register */ 156 #define UFSHCI_REG_UTRLDBR 0x58 /* RWS */ 157 /* Clear Register */ 158 #define UFSHCI_REG_UTRLCLR 0x5C /* WO */ 159 /* Run-Stop Register */ 160 #define UFSHCI_REG_UTRLRSR 0x60 /* RW */ 161 #define UFSHCI_REG_UTRLRSR_STOP 0x00 162 #define UFSHCI_REG_UTRLRSR_START 0x01 163 /* Completion Notification Register */ 164 #define UFSHCI_REG_UTRLCNR 0x64 /* RWC */ 165 166 /* 167 * UTP Task Management Request List Registers 168 */ 169 170 /* Base Address */ 171 #define UFSHCI_REG_UTMRLBA 0x70 /* RW */ 172 /* Base Address Upper 32-bits */ 173 #define UFSHCI_REG_UTMRLBAU 0x74 /* RW */ 174 /* Door Bell Register */ 175 #define UFSHCI_REG_UTMRLDBR 0x78 /* RWS */ 176 /* Clear Register */ 177 #define UFSHCI_REG_UTMRLCLR 0x7C /* WO */ 178 /* Run-Stop Register */ 179 #define UFSHCI_REG_UTMRLRSR 0x80 /* RW */ 180 #define UFSHCI_REG_UTMRLRSR_STOP 0x00 181 #define UFSHCI_REG_UTMRLRSR_START 0x01 182 183 /* 184 * UIC Command Registers 185 */ 186 187 /* UIC Command Register */ 188 #define UFSHCI_REG_UICCMD 0x90 189 #define UFSHCI_REG_UICCMD_CMDOP_DME_GET 0x01 /* RW */ 190 #define UFSHCI_REG_UICCMD_CMDOP_DME_SET 0x02 /* RW */ 191 #define UFSHCI_REG_UICCMD_CMDOP_DME_PEER_GET 0x03 /* RW */ 192 #define UFSHCI_REG_UICCMD_CMDOP_DME_PEER_SET 0x04 /* RW */ 193 #define UFSHCI_REG_UICCMD_CMDOP_DME_POWERON 0x10 /* RW */ 194 #define UFSHCI_REG_UICCMD_CMDOP_DME_POWEROFF 0x11 /* RW */ 195 #define UFSHCI_REG_UICCMD_CMDOP_DME_ENABLE 0x12 /* RW */ 196 #define UFSHCI_REG_UICCMD_CMDOP_DME_RESET 0x14 /* RW */ 197 #define UFSHCI_REG_UICCMD_CMDOP_DME_ENDPOINTRESET 0x15 /* RW */ 198 #define UFSHCI_REG_UICCMD_CMDOP_DME_LINKSTARTUP 0x16 /* RW */ 199 #define UFSHCI_REG_UICCMD_CMDOP_DME_HIBERNATE_ENTER 0x17 /* RW */ 200 #define UFSHCI_REG_UICCMD_CMDOP_DME_HIBERNATE_EXIT 0x18 /* RW */ 201 #define UFSHCI_REG_UICCMD_CMDOP_DME_TEST_MODE 0x1A /* RW */ 202 /* UIC Command Argument 1 */ 203 #define UFSHCI_REG_UICCMDARG1 0x94 204 /* UIC Command Argument 2 */ 205 #define UFSHCI_REG_UICCMDARG2 0x98 206 /* UIC Command Argument 3 */ 207 #define UFSHCI_REG_UICCMDARG3 0x9C 208 209 /* 210 * Vendor Specific Registers (0xC0 - 0xFF) 211 */ 212 213 /* 214 * UTP Transfer Request Descriptor Structure 215 */ 216 217 /* Command Type (CT) */ 218 #define UFSHCI_UTRD_DW0_CT_UFS (1 << 28) /* UFS Storage */ 219 /* Data Direction (DD) */ 220 #define UFSHCI_UTRD_DW0_DD_NO (0 << 25) /* No transfer */ 221 #define UFSHCI_UTRD_DW0_DD_I2T (1 << 25) /* From Initiator to Target */ 222 #define UFSHCI_UTRD_DW0_DD_T2I (2 << 25) /* From Target to Initiator */ 223 /* Interrupt (I) */ 224 #define UFSHCI_UTRD_DW0_I_REG (0 << 24) /* Regular Command */ 225 #define UFSHCI_UTRD_DW0_I_INT (1 << 24) /* Interrupt Command */ 226 /* Crypto Enable (CE) */ 227 #define UFSHCI_UTRD_DW0_CE_DISABLE (0 << 23) /* Disable Crypto */ 228 #define UFSHCI_UTRD_DW0_CE_ENABLE (1 << 23) /* Enable Crypto */ 229 /* Crypto Configuration Index (CCI) */ 230 #define UFSHCI_UTRD_DW0_CCI(x) (x & 0x000000ff) 231 232 /* Data Unit Number Upper 32-bits (DUNL) */ 233 #define UFSHCI_UTRD_DW1_DUNL(x) (x << 0) 234 235 /* Overall Command Status (OCS) */ 236 #define UFSHCI_UTRD_DW2_OCS(x) (x & 0x000000ff) 237 #define UFSHCI_UTRD_DW2_OCS_SUCCESS 0x00 /* Success */ 238 #define UFSHCI_UTRD_DW2_OCS_ICTA 0x01 /* Invalid Command Table Attr. */ 239 #define UFSHCI_UTRD_DW2_OCS_IPA 0x02 /* Invalid PRDT Attr. */ 240 #define UFSHCI_UTRD_DW2_OCS_MDBS 0x03 /* Mismatch Data Buffer Size */ 241 #define UFSHCI_UTRD_DW2_OCS_MRUS 0x04 /* Mismatch Response UPIU Size */ 242 #define UFSHCI_UTRD_DW2_OCS_CF 0x05 /* Communication Failure */ 243 #define UFSHCI_UTRD_DW2_OCS_ABRT 0x06 /* Aborted */ 244 #define UFSHCI_UTRD_DW2_OCS_FE 0x07 /* Fatal Error */ 245 #define UFSHCI_UTRD_DW2_OCS_DFE 0x08 /* Device Fatal Error */ 246 #define UFSHCI_UTRD_DW2_OCS_ICC 0x09 /* Invalid Crypto Configuration */ 247 #define UFSHCI_UTRD_DW2_OCS_GCE 0x0A /* General Crypto Error */ 248 #define UFSHCI_UTRD_DW2_OCS_IOV 0x0F /* Invalid OCS Value */ 249 250 /* Data Unit Number Upper 32-bits Upper 32-bits (DUNU) */ 251 #define UFSHCI_UTRD_DW3_DUNU(x) (x << 0) 252 253 /* UTP Command Descriptor Base Address (UCDBA) */ 254 #define UFSHCI_UTRD_DW4_UCDBA(x) (x << 7) 255 256 /* UTP Command Descriptor Base Address Upper 32-bits (UCDBAU) */ 257 #define UFSHCI_UTRD_DW5_UCDBAU(x) (x << 0) 258 259 /* Response UPIU Offset (RUO) */ 260 #define UFSHCI_UTRD_DW6_RUO(x) (x << 16) 261 /* Response UPIU Length (RUL) */ 262 #define UFSHCI_UTRD_DW6_RUL(x) (x & 0x0000ffff) 263 264 /* PRDT Offset (PRDTO) */ 265 #define UFSHCI_UTRD_DW7_PRDTO(x) (x << 16) 266 /* PRDT Length (PRDTL) */ 267 #define UFSHCI_UTRD_DW7_PRDTL(x) (x & 0x0000ffff) 268 269 struct ufshci_utrd { 270 uint32_t dw0; /* CT, DD, I, CE, CCI */ 271 uint32_t dw1; /* Data Unit Number Lower 32-bits (DUNL) */ 272 uint32_t dw2; /* OCS */ 273 uint32_t dw3; /* Data Unit Number Upper 32-bits (DUNU) */ 274 uint32_t dw4; /* UTP Cmd. Desc. Base Addr. Lower 32-bits (UCDBA) */ 275 uint32_t dw5; /* UTP Cmd. Desc. Base Addr. Upper 32-bits (UCDBAU) */ 276 uint32_t dw6; /* RUO, RUL */ 277 uint32_t dw7; /* PRDTO, PRDTL */ 278 } __packed; 279 280 /* 281 * UTP Command Descriptor, PRDT (Physical Region Description Table) Structure 282 */ 283 284 /* Data Base Address (DBA) */ 285 #define UFSHCI_UCD_DW0_DBA(x) (x & 0xfffffffc) 286 287 /* Data Byte Count (DBC) */ 288 #define UFSHCI_UCD_DW3_DBC(x) (x & 0x0003ffff) 289 290 struct ufshci_ucd_prdt { 291 uint32_t dw0; /* Data base Address Lower 32-bits (DBA) */ 292 uint32_t dw1; /* Data base Address Upper 32-bits (DBAU) */ 293 uint32_t dw2; /* Reserved */ 294 uint32_t dw3; /* Data Byte Count (DBC) */ 295 } __packed; 296 297 /* 298 * UTP Task Management Request Descriptor Structure 299 */ 300 301 /* Interrupt (I) */ 302 #define UFSHCI_UTMRD_DW0_I_DISABLE (0 << 24) 303 #define UFSHCI_UTMRD_DW0_I_ENABLE (1 << 24) 304 305 /* Overall Command Status (OCS) */ 306 #define UFSHCI_UTMRD_DW2_OCS(x) (x & 0x000000ff) 307 #define UFSHCI_UTMRD_DW2_OCS_SUCCESS 0x00 /* Success */ 308 #define UFSHCI_UTMRD_DW2_OCS_ICTA 0x01 /* Invalid Command Table Attr. */ 309 #define UFSHCI_UTMRD_DW2_OCS_IPA 0x02 /* Invalid PRDT Attr. */ 310 #define UFSHCI_UTMRD_DW2_OCS_MDBS 0x03 /* Mismatch Data Buffer Size */ 311 #define UFSHCI_UTMRD_DW2_OCS_MRUS 0x04 /* Mismatch Response UPIU Size */ 312 #define UFSHCI_UTMRD_DW2_OCS_CF 0x05 /* Communication Failure */ 313 #define UFSHCI_UTMRD_DW2_OCS_ABRT 0x06 /* Aborted */ 314 #define UFSHCI_UTMRD_DW2_OCS_FE 0x07 /* Fatal Error */ 315 #define UFSHCI_UTMRD_DW2_OCS_DFE 0x08 /* Device Fatal Error */ 316 #define UFSHCI_UTMRD_DW2_OCS_ICC 0x09 /* Invalid Crypto Configuration */ 317 #define UFSHCI_UTMRD_DW2_OCS_GCE 0x0A /* General Crypto Error */ 318 #define UFSHCI_UTMRD_DW2_OCS_IOV 0x0F /* Invalid OCS Value */ 319 320 struct ufshci_utmrd { 321 uint32_t dw0; /* I */ 322 uint32_t dw1; /* Reserved */ 323 uint32_t dw2; /* OCS */ 324 uint32_t dw3; /* Reserved */ 325 uint8_t dw4_w11[32]; /* Task Management Request UPIU */ 326 uint8_t dw12_dw19[32]; /* Task Management Response UPIU */ 327 } __packed; 328 329 /* 330 * **************************************************************************** 331 * Universal Flash Storage (UFS) Version 2.1 Specs from JESD220C 332 * **************************************************************************** 333 */ 334 335 /* UPIU structures are in Big Endian! */ 336 337 #define UPIU_TC_I2T_NOP_OUT 0x00 338 #define UPIU_TC_I2T_COMMAND 0x01 339 #define UPIU_TC_I2T_DATA_OUT 0x02 340 #define UPIU_TC_I2T_TMR 0x04 341 #define UPIU_TC_I2T_QUERY_REQUEST 0x16 342 #define UPIU_TC_T2I_NOP_IN 0x20 343 #define UPIU_TC_T2I_RESPONSE 0x21 344 #define UPIU_TC_T2I_DATA_IN 0x22 345 #define UPIU_TC_T2I_TMR 0x24 346 #define UPIU_TC_T2I_QUERY_RESPONSE 0x36 347 #define UPIU_TC_T2I_REJECT 0x3f 348 349 #define UPIU_SCSI_RSP_INQUIRY_SIZE 36 350 #define UPIU_SCSI_RSP_CAPACITY16_SIZE 32 351 #define UPIU_SCSI_RSP_CAPACITY_SIZE 8 352 353 struct upiu_hdr { 354 uint8_t tc; /* Transaction Code */ 355 uint8_t flags; 356 uint8_t lun; 357 uint8_t task_tag; 358 uint8_t cmd_set_type; 359 uint8_t query; 360 uint8_t response; 361 uint8_t status; 362 uint8_t ehs_len; 363 uint8_t device_info; 364 uint16_t ds_len; /* Data Segment Length */ 365 } __packed; 366 367 struct upiu_command { 368 struct upiu_hdr hdr; 369 uint32_t expected_xfer_len; 370 uint8_t cdb[16]; 371 } __packed; 372 373 struct upiu_response { 374 struct upiu_hdr hdr; 375 uint32_t residual_xfer_len; 376 uint8_t cdb[16]; 377 } __packed; 378 379 struct ufshci_ucd { 380 struct upiu_command cmd; 381 struct upiu_response rsp; 382 struct ufshci_ucd_prdt prdt[UFSHCI_UCD_PRDT_MAX_SEGS]; 383 } __packed __aligned(128); 384