Home
last modified time | relevance | path

Searched refs:UINT_TO_FP (Results 1 – 25 of 37) sorted by relevance

12

/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp683 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
769 { ISD::UINT_TO_FP, MVT::f32, MVT::i1, 2 }, in getCastInstrCost()
771 { ISD::UINT_TO_FP, MVT::f64, MVT::i1, 2 }, in getCastInstrCost()
773 { ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 }, in getCastInstrCost()
775 { ISD::UINT_TO_FP, MVT::f64, MVT::i8, 2 }, in getCastInstrCost()
777 { ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 }, in getCastInstrCost()
779 { ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 }, in getCastInstrCost()
781 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 2 }, in getCastInstrCost()
783 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 2 }, in getCastInstrCost()
785 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 10 }, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp175 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in addTypeForNEON()
180 setOperationAction(ISD::UINT_TO_FP, VT, Expand); in addTypeForNEON()
306 setOperationAction(ISD::UINT_TO_FP, VT, Expand); in addMVEVectorTypes()
458 setOperationAction(ISD::UINT_TO_FP, VT, Expand); in addMVEVectorTypes()
469 setOperationAction(ISD::UINT_TO_FP, MVT::v2i1, Expand); in addMVEVectorTypes()
943 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); in ARMTargetLowering()
944 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom); in ARMTargetLowering()
1059 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in ARMTargetLowering()
5977 case ISD::UINT_TO_FP: in LowerVectorINT_TO_FP()
5979 Opc = ISD::UINT_TO_FP; in LowerVectorINT_TO_FP()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2178 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, in getCastInstrCost()
2179 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, in getCastInstrCost()
2296 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, in getCastInstrCost()
2297 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
2298 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, in getCastInstrCost()
2299 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, in getCastInstrCost()
2300 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, in getCastInstrCost()
2301 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, in getCastInstrCost()
2302 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, in getCastInstrCost()
2303 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, in getCastInstrCost()
[all …]
H A DX86ISelLowering.cpp233 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote); in X86TargetLowering()
944 setOperationAction(ISD::UINT_TO_FP, VT, Expand); in X86TargetLowering()
2332 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom); in X86TargetLowering()
2396 ISD::UINT_TO_FP, in X86TargetLowering()
21045 Op.getOpcode() == ISD::UINT_TO_FP) && in LowerI64IntToFP_AVX512DQ()
21087 Op.getOpcode() == ISD::UINT_TO_FP) && in LowerI64IntToFP16()
21128 case ISD::UINT_TO_FP: in useVectorCast()
21715 Res = DAG.getNode(ISD::UINT_TO_FP, DL, WideVT, V); in lowerUINT_TO_FP_vXi32()
33906 case ISD::UINT_TO_FP: in ReplaceNodeResults()
53973 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P); in combineUIntToFP()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp1886 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
1887 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
1888 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
1894 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
1895 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
1896 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
1901 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
1902 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
1908 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
1918 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp510 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
511 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
512 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
940 ISD::UINT_TO_FP}); in AArch64TargetLowering()
1222 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in AArch64TargetLowering()
1313 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in AArch64TargetLowering()
1788 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in addTypeForStreamingSVE()
1913 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in addTypeForFixedLengthSVE()
5947 case ISD::UINT_TO_FP: in LowerOperation()
15895 (Opc != ISD::SINT_TO_FP && Opc != ISD::UINT_TO_FP)) in performFDivCombine()
[all …]
/openbsd/gnu/llvm/llvm/include/llvm/IR/
H A DConstrainedOps.def59 DAG_INSTRUCTION(UIToFP, 1, 1, experimental_constrained_uitofp, UINT_TO_FP)
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h774 UINT_TO_FP, enumerator
/openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp430 case ISD::UINT_TO_FP: in LegalizeOp()
546 case ISD::UINT_TO_FP: in Promote()
619 unsigned Opc = (Node->getOpcode() == ISD::UINT_TO_FP || in PromoteINT_TO_FP()
769 case ISD::UINT_TO_FP: in Expand()
H A DSelectionDAGDumper.cpp359 case ISD::UINT_TO_FP: return "uint_to_fp"; in getOperationName()
H A DLegalizeFloatTypes.cpp138 case ISD::UINT_TO_FP: R = SoftenFloatRes_XINT_TO_FP(N); break; in SoftenFloatResult()
1275 case ISD::UINT_TO_FP: ExpandFloatRes_XINT_TO_FP(N, Lo, Hi); break; in ExpandFloatResult()
2300 case ISD::UINT_TO_FP: R = PromoteFloatRes_XINT_TO_FP(N); break; in PromoteFloatResult()
2664 case ISD::UINT_TO_FP: R = SoftPromoteHalfRes_XINT_TO_FP(N); break; in SoftPromoteHalfResult()
H A DLegalizeDAG.cpp1005 case ISD::UINT_TO_FP: in LegalizeOp()
2541 unsigned UIntOp = IsStrict ? ISD::STRICT_UINT_TO_FP : ISD::UINT_TO_FP; in PromoteLegalINT_TO_FP()
2984 case ISD::UINT_TO_FP: in ExpandNode()
4275 case ISD::UINT_TO_FP: { in ConvertNodeToLibcall()
4484 if (Node->getOpcode() == ISD::UINT_TO_FP || in PromoteNode()
4559 case ISD::UINT_TO_FP: in PromoteNode()
H A DLegalizeVectorTypes.cpp111 case ISD::UINT_TO_FP: in ScalarizeVectorResult()
649 case ISD::UINT_TO_FP: in ScalarizeVectorOperand()
1067 case ISD::UINT_TO_FP: in SplitVectorResult()
2838 case ISD::UINT_TO_FP: in SplitVectorOperand()
4064 case ISD::UINT_TO_FP: in WidenVectorResult()
5822 case ISD::UINT_TO_FP: in WidenVectorOperand()
/openbsd/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp168 setTargetDAGCombine({ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_EXTEND, in WebAssemblyTargetLowering()
254 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}) in WebAssemblyTargetLowering()
1889 case ISD::UINT_TO_FP: in LowerConvertLow()
2366 assert(N->getOpcode() == ISD::UINT_TO_FP || in performVectorExtendToFPCombine()
2380 N->getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; in performVectorExtendToFPCombine()
2670 case ISD::UINT_TO_FP: in PerformDAGCombine()
/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp254 setOperationAction(ISD::UINT_TO_FP, T, Custom); in initializeHVXLowering()
327 setOperationAction(ISD::UINT_TO_FP, T, Custom); in initializeHVXLowering()
428 setOperationAction(ISD::UINT_TO_FP, VecTy, Custom); in initializeHVXLowering()
2303 Op.getOpcode() == ISD::UINT_TO_FP); in LowerHvxIntToFp()
2677 Opc == ISD::SINT_TO_FP || Opc == ISD::UINT_TO_FP); in EqualizeFpIntConversion()
2828 assert(Opc == ISD::SINT_TO_FP || Opc == ISD::UINT_TO_FP); in ExpandHvxIntToFp()
3154 case ISD::UINT_TO_FP: in LowerHvxOperation()
3236 case ISD::UINT_TO_FP: return LowerHvxIntToFp(Op, DAG); in LowerHvxOperation()
3403 case ISD::UINT_TO_FP: in LowerHvxOperationWrapper()
H A DHexagonISelLowering.cpp1769 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1770 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1771 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp409 {ISD::UINT_TO_FP, ISD::SINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in AMDGPUTargetLowering()
431 ISD::UINT_TO_FP, ISD::SDIV, ISD::UDIV, in AMDGPUTargetLowering()
1268 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); in LowerOperation()
1709 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerDIVREM24()
1850 SDValue Cvt_Lo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Lo); in LowerUDIVREM64()
1851 SDValue Cvt_Hi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Hi); in LowerUDIVREM64()
2512 (Signed && Subtarget->isGCN()) ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerINT_TO_FP32()
2549 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, in LowerINT_TO_FP64()
2552 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo); in LowerINT_TO_FP64()
2574 return DAG.getNode(ISD::UINT_TO_FP, DL, DestVT, Ext); in LowerUINT_TO_FP()
H A DR600ISelLowering.cpp1733 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) { in PerformDAGCombine()
1734 return DAG.getNode(ISD::UINT_TO_FP, DL, N->getValueType(0), in PerformDAGCombine()
/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp258 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1, in PPCTargetLowering()
278 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
527 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
541 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
1373 setTargetDAGCombine(ISD::UINT_TO_FP); in PPCTargetLowering()
8367 UI->getOpcode() != ISD::UINT_TO_FP && in directMoveIsProfitable()
11344 case ISD::UINT_TO_FP: in LowerOperation()
14560 FirstInput.getOpcode() != ISD::UINT_TO_FP) in DAGCombineBuildVector()
14563 N->getOperand(1).getOpcode() != ISD::UINT_TO_FP) in DAGCombineBuildVector()
14602 N->getOpcode() == ISD::UINT_TO_FP) && in combineFPToIntToFP()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1653 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1655 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
3215 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this, in LowerOperation()
3588 case ISD::UINT_TO_FP: in ReplaceNodeResults()
/openbsd/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp179 setOperationAction(ISD::UINT_TO_FP, GRLenVT, Expand); in LoongArchTargetLowering()
183 setOperationAction(ISD::UINT_TO_FP, GRLenVT, Custom); in LoongArchTargetLowering()
246 case ISD::UINT_TO_FP: in LowerOperation()
/openbsd/gnu/llvm/llvm/lib/Target/VE/
H A DVEISelLowering.cpp214 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote); // use i64 in initSPUActions()
216 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); in initSPUActions()
2917 case ISD::UINT_TO_FP: in isI32Insn()
/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp271 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote); in SystemZTargetLowering()
272 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); in SystemZTargetLowering()
417 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal); in SystemZTargetLowering()
418 setOperationAction(ISD::UINT_TO_FP, MVT::v2f64, Legal); in SystemZTargetLowering()
437 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal); in SystemZTargetLowering()
438 setOperationAction(ISD::UINT_TO_FP, MVT::v4f32, Legal); in SystemZTargetLowering()
660 ISD::UINT_TO_FP, in SystemZTargetLowering()
6781 (Opcode == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND); in combineINT_TO_FP()
7146 case ISD::UINT_TO_FP: return combineINT_TO_FP(N, DCI); in PerformDAGCombine()
/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp962 case ISD::UINT_TO_FP: in getCastInstrCost()
/openbsd/gnu/llvm/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1838 case UIToFP: return ISD::UINT_TO_FP; in InstructionOpcodeToISD()

12