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Searched refs:UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK (Results 1 – 17 of 17) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dce/
H A Ddce_10_0_sh_mask.h2793 #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 macro
H A Ddce_11_0_sh_mask.h2777 #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 macro
H A Ddce_11_2_sh_mask.h3017 #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 macro
H A Ddce_12_0_sh_mask.h9121 #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h39869 #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK … macro
H A Ddcn_2_1_0_sh_mask.h43164 #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK … macro
H A Ddcn_3_0_1_sh_mask.h35878 #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK … macro
H A Ddcn_3_2_1_sh_mask.h39833 #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK … macro
H A Ddcn_3_1_2_sh_mask.h44552 #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK … macro
H A Ddcn_3_1_5_sh_mask.h42655 #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK … macro
H A Ddcn_3_1_6_sh_mask.h45612 #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK … macro
H A Ddcn_3_0_2_sh_mask.h42450 #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK … macro
H A Ddcn_2_0_0_sh_mask.h48643 #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK … macro
H A Ddcn_3_0_0_sh_mask.h49016 #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_4_2_0_sh_mask.h3580 #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK … macro
H A Ddpcs_4_2_2_sh_mask.h3701 #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK … macro
H A Ddpcs_4_2_3_sh_mask.h3731 #define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK … macro