1 /* $OpenBSD: if_urtwreg.h,v 1.16 2014/09/01 16:02:06 mpi Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Martynas Venckus <martynas@openbsd.org> 5 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Known hardware revisions. 22 */ 23 #define URTW_HWREV_8187 0x01 24 #define URTW_HWREV_8187_B 0x02 25 #define URTW_HWREV_8187_D 0x04 26 #define URTW_HWREV_8187B 0x08 27 #define URTW_HWREV_8187B_B 0x10 28 #define URTW_HWREV_8187B_D 0x20 29 #define URTW_HWREV_8187B_E 0x40 30 31 /* 32 * Registers specific to RTL8187 and RTL8187B. 33 */ 34 #define URTW_MAC0 0x0000 /* 1 byte */ 35 #define URTW_MAC1 0x0001 /* 1 byte */ 36 #define URTW_MAC2 0x0002 /* 1 byte */ 37 #define URTW_MAC3 0x0003 /* 1 byte */ 38 #define URTW_MAC4 0x0004 /* 1 byte */ 39 #define URTW_MAC5 0x0005 /* 1 byte */ 40 #define URTW_8187_BRSR 0x002c /* 2 byte */ 41 #define URTW_BRSR_MBR_8185 (0x0fff) 42 #define URTW_8187B_EIFS 0x002d /* 1 byte */ 43 #define URTW_BSSID 0x002e /* 6 byte */ 44 #define URTW_RESP_RATE 0x0034 /* 1 byte */ 45 #define URTW_8187B_BRSR 0x0034 /* 2 byte */ 46 #define URTW_RESP_MAX_RATE_SHIFT (4) 47 #define URTW_RESP_MIN_RATE_SHIFT (0) 48 #define URTW_8187_EIFS 0x0035 /* 1 byte */ 49 #define URTW_INTR_MASK 0x003c /* 2 byte */ 50 #define URTW_CMD 0x0037 /* 1 byte */ 51 #define URTW_CMD_TX_ENABLE (0x4) 52 #define URTW_CMD_RX_ENABLE (0x8) 53 #define URTW_CMD_RST (0x10) 54 #define URTW_TX_CONF 0x0040 /* 4 byte */ 55 #define URTW_TX_HWREV_MASK (7 << 25) 56 #define URTW_TX_HWREV_8187_D (5 << 25) 57 #define URTW_TX_HWREV_8187B_D (6 << 25) 58 #define URTW_TX_DURPROCMODE (1 << 30) 59 #define URTW_TX_DISREQQSIZE (1 << 28) 60 #define URTW_TX_SHORTRETRY (7 << 8) 61 #define URTW_TX_LONGRETRY (7 << 0) 62 #define URTW_TX_LOOPBACK_SHIFT (17) 63 #define URTW_TX_LOOPBACK_NONE (0 << URTW_TX_LOOPBACK_SHIFT) 64 #define URTW_TX_LOOPBACK_MAC (1 << URTW_TX_LOOPBACK_SHIFT) 65 #define URTW_TX_LOOPBACK_BASEBAND (2 << URTW_TX_LOOPBACK_SHIFT) 66 #define URTW_TX_LOOPBACK_CONTINUE (3 << URTW_TX_LOOPBACK_SHIFT) 67 #define URTW_TX_LOOPBACK_MASK (0x60000) 68 #define URTW_TX_DPRETRY_MASK (0xff00) 69 #define URTW_TX_RTSRETRY_MASK (0xff) 70 #define URTW_TX_DPRETRY_SHIFT (0) 71 #define URTW_TX_RTSRETRY_SHIFT (8) 72 #define URTW_TX_NOCRC (0x10000) 73 #define URTW_TX_MXDMA_MASK (0xe00000) 74 #define URTW_TX_MXDMA_1024 (6 << URTW_TX_MXDMA_SHIFT) 75 #define URTW_TX_MXDMA_2048 (7 << URTW_TX_MXDMA_SHIFT) 76 #define URTW_TX_MXDMA_SHIFT (21) 77 #define URTW_TX_CWMIN (1U << 31) 78 #define URTW_TX_DISCW (1U << 20) 79 #define URTW_TX_SWPLCPLEN (1U << 24) 80 #define URTW_TX_NOICV (0x80000) 81 #define URTW_RX 0x0044 /* 4 byte */ 82 #define URTW_RX_9356SEL (1 << 6) 83 #define URTW_RX_FILTER_MASK \ 84 (URTW_RX_FILTER_ALLMAC | URTW_RX_FILTER_NICMAC | URTW_RX_FILTER_MCAST | \ 85 URTW_RX_FILTER_BCAST | URTW_RX_FILTER_CRCERR | URTW_RX_FILTER_ICVERR | \ 86 URTW_RX_FILTER_DATA | URTW_RX_FILTER_CTL | URTW_RX_FILTER_MNG | \ 87 (1 << 21) | \ 88 URTW_RX_FILTER_PWR | URTW_RX_CHECK_BSSID) 89 #define URTW_RX_FILTER_ALLMAC (0x00000001) 90 #define URTW_RX_FILTER_NICMAC (0x00000002) 91 #define URTW_RX_FILTER_MCAST (0x00000004) 92 #define URTW_RX_FILTER_BCAST (0x00000008) 93 #define URTW_RX_FILTER_CRCERR (0x00000020) 94 #define URTW_RX_FILTER_ICVERR (0x00001000) 95 #define URTW_RX_FILTER_DATA (0x00040000) 96 #define URTW_RX_FILTER_CTL (0x00080000) 97 #define URTW_RX_FILTER_MNG (0x00100000) 98 #define URTW_RX_FILTER_PWR (0x00400000) 99 #define URTW_RX_CHECK_BSSID (0x00800000) 100 #define URTW_RX_FIFO_THRESHOLD_MASK ((1 << 13) | (1 << 14) | (1 << 15)) 101 #define URTW_RX_FIFO_THRESHOLD_SHIFT (13) 102 #define URTW_RX_FIFO_THRESHOLD_128 (3) 103 #define URTW_RX_FIFO_THRESHOLD_256 (4) 104 #define URTW_RX_FIFO_THRESHOLD_512 (5) 105 #define URTW_RX_FIFO_THRESHOLD_1024 (6) 106 #define URTW_RX_FIFO_THRESHOLD_NONE (7 << URTW_RX_FIFO_THRESHOLD_SHIFT) 107 #define URTW_RX_AUTORESETPHY (1 << URTW_RX_AUTORESETPHY_SHIFT) 108 #define URTW_RX_AUTORESETPHY_SHIFT (28) 109 #define URTW_MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10)) 110 #define URTW_MAX_RX_DMA_2048 (7 << URTW_MAX_RX_DMA_SHIFT) 111 #define URTW_MAX_RX_DMA_1024 (6) 112 #define URTW_MAX_RX_DMA_SHIFT (10) 113 #define URTW_RCR_ONLYERLPKT (1U << 31) 114 #define URTW_INT_TIMEOUT 0x0048 /* 4 byte */ 115 #define URTW_EPROM_CMD 0x0050 /* 1 byte */ 116 #define URTW_EPROM_CMD_NORMAL (0x0) 117 #define URTW_EPROM_CMD_NORMAL_MODE \ 118 (URTW_EPROM_CMD_NORMAL << URTW_EPROM_CMD_SHIFT) 119 #define URTW_EPROM_CMD_LOAD (0x1) 120 #define URTW_EPROM_CMD_PROGRAM (0x2) 121 #define URTW_EPROM_CMD_PROGRAM_MODE \ 122 (URTW_EPROM_CMD_PROGRAM << URTW_EPROM_CMD_SHIFT) 123 #define URTW_EPROM_CMD_CONFIG (0x3) 124 #define URTW_EPROM_CMD_SHIFT (6) 125 #define URTW_EPROM_CMD_MASK ((1 << 7) | (1 << 6)) 126 #define URTW_EPROM_READBIT (0x1) 127 #define URTW_EPROM_WRITEBIT (0x2) 128 #define URTW_EPROM_CK (0x4) 129 #define URTW_EPROM_CS (0x8) 130 #define URTW_CONFIG1 0x0052 /* 1 byte */ 131 #define URTW_CONFIG2 0x0053 /* 1 byte */ 132 #define URTW_ANAPARAM 0x0054 /* 4 byte */ 133 #define URTW_8187_8225_ANAPARAM_ON (0xa0000a59) 134 #define URTW_8187B_8225_ANAPARAM_ON (0x45090658) 135 #define URTW_MSR 0x0058 /* 1 byte */ 136 #define URTW_MSR_LINK_MASK ((1 << 2) | (1 << 3)) 137 #define URTW_MSR_LINK_SHIFT (2) 138 #define URTW_MSR_LINK_NONE (0 << URTW_MSR_LINK_SHIFT) 139 #define URTW_MSR_LINK_ADHOC (1 << URTW_MSR_LINK_SHIFT) 140 #define URTW_MSR_LINK_STA (2 << URTW_MSR_LINK_SHIFT) 141 #define URTW_MSR_LINK_HOSTAP (3 << URTW_MSR_LINK_SHIFT) 142 #define URTW_MSR_LINK_ENEDCA (4 << URTW_MSR_LINK_SHIFT) 143 #define URTW_CONFIG3 0x0059 /* 1 byte */ 144 #define URTW_CONFIG3_ANAPARAM_WRITE (0x40) 145 #define URTW_CONFIG3_ANAPARAM_W_SHIFT (6) 146 #define URTW_CONFIG3_GNT_SELECT (0x80) 147 #define URTW_PSR 0x005e /* 1 byte */ 148 #define URTW_ANAPARAM2 0x0060 /* 4 byte */ 149 #define URTW_8187_8225_ANAPARAM2_ON (0x860c7312) 150 #define URTW_8187B_8225_ANAPARAM2_ON (0x727f3f52) 151 #define URTW_BEACON_INTERVAL 0x0070 /* 2 byte */ 152 #define URTW_ATIM_WND 0x0072 /* 2 byte */ 153 #define URTW_BEACON_INTERVAL_TIME 0x0074 /* 2 byte */ 154 #define URTW_ATIM_TR_ITV 0x0076 /* 2 byte */ 155 #define URTW_RF_PINS_OUTPUT 0x0080 /* 2 byte */ 156 #define URTW_BB_HOST_BANG_CLK (1 << 1) 157 #define URTW_BB_HOST_BANG_EN (1 << 2) 158 #define URTW_BB_HOST_BANG_RW (1 << 3) 159 #define URTW_RF_PINS_ENABLE 0x0082 /* 2 byte */ 160 #define URTW_RF_PINS_SELECT 0x0084 /* 2 byte */ 161 #define URTW_RF_PINS_INPUT 0x0086 /* 2 byte */ 162 #define URTW_RF_PARA 0x0088 /* 4 byte */ 163 #define URTW_RF_TIMING 0x008c /* 4 byte */ 164 #define URTW_GP_ENABLE 0x0090 /* 1 byte */ 165 #define URTW_GPIO 0x0091 /* 1 byte */ 166 #define URTW_HSSI_PARA 0x0094 /* 4 byte */ 167 #define URTW_TX_AGC_CTL 0x009c /* 1 byte */ 168 #define URTW_TX_AGC_CTL_PERPACKET_GAIN (0x1) 169 #define URTW_TX_AGC_CTL_PERPACKET_ANTSEL (0x2) 170 #define URTW_TX_AGC_CTL_FEEDBACK_ANT (0x4) 171 #define URTW_TX_GAIN_CCK 0x009d /* 1 byte */ 172 #define URTW_TX_GAIN_OFDM 0x009e /* 1 byte */ 173 #define URTW_TX_ANTENNA 0x009f /* 1 byte */ 174 #define URTW_WPA_CONFIG 0x00b0 /* 1 byte */ 175 #define URTW_SIFS 0x00b4 /* 1 byte */ 176 #define URTW_DIFS 0x00b5 /* 1 byte */ 177 #define URTW_SLOT 0x00b6 /* 1 byte */ 178 #define URTW_CW_CONF 0x00bc /* 1 byte */ 179 #define URTW_CW_CONF_PERPACKET_RETRY (0x2) 180 #define URTW_CW_CONF_PERPACKET_CW (0x1) 181 #define URTW_CW_VAL 0x00bd /* 1 byte */ 182 #define URTW_RATE_FALLBACK 0x00be /* 1 byte */ 183 #define URTW_RATE_FALLBACK_ENABLE (0x80) 184 #define URTW_ACM_CONTROL 0x00bf /* 1 byte */ 185 #define URTW_8187B_HWREV 0x00e1 /* 1 byte */ 186 #define URTW_8187B_HWREV_8187B_B (0x0) 187 #define URTW_8187B_HWREV_8187B_D (0x1) 188 #define URTW_8187B_HWREV_8187B_E (0x2) 189 #define URTW_INT_MIG 0x00e2 /* 2 byte */ 190 #define URTW_TID_AC_MAP 0x00e8 /* 2 byte */ 191 #define URTW_ANAPARAM3 0x00ee /* 4 byte */ 192 #define URTW_8187B_8225_ANAPARAM3_ON (0x0) 193 #define URTW_TALLY_SEL 0x00fc /* 1 byte */ 194 #define URTW_AC_VO 0x00f0 /* 1 byte */ 195 #define URTW_AC_VI 0x00f4 /* 1 byte */ 196 #define URTW_AC_BE 0x00f8 /* 1 byte */ 197 #define URTW_AC_BK 0x00fc /* 1 byte */ 198 #define URTW_FEMR 0x01d4 /* 2 byte */ 199 #define URTW_ARFR 0x01e0 /* 2 byte */ 200 #define URTW_RFSW_CTRL 0x0272 /* 2 byte */ 201 202 /* for EEPROM */ 203 #define URTW_EPROM_TXPW_BASE 0x05 204 #define URTW_EPROM_RFCHIPID 0x06 205 #define URTW_EPROM_RFCHIPID_RTL8225U (5) 206 #define URTW_EPROM_MACADDR 0x07 207 #define URTW_EPROM_TXPW0 0x16 208 #define URTW_EPROM_TXPW2 0x1b 209 #define URTW_EPROM_TXPW1 0x3d 210 #define URTW_EPROM_SWREV 0x3f 211 #define URTW_EPROM_CID_MASK (0xff) 212 #define URTW_EPROM_CID_RSVD0 (0x00) 213 #define URTW_EPROM_CID_RSVD1 (0xff) 214 #define URTW_EPROM_CID_ALPHA0 (0x01) 215 #define URTW_EPROM_CID_SERCOMM_PS (0x02) 216 #define URTW_EPROM_CID_HW_LED (0x03) 217 218 /* LED */ 219 #define URTW_CID_DEFAULT 0 220 #define URTW_CID_8187_ALPHA0 1 221 #define URTW_CID_8187_SERCOMM_PS 2 222 #define URTW_CID_8187_HW_LED 3 223 #define URTW_SW_LED_MODE0 0 224 #define URTW_SW_LED_MODE1 1 225 #define URTW_SW_LED_MODE2 2 226 #define URTW_SW_LED_MODE3 3 227 #define URTW_HW_LED 4 228 #define URTW_LED_CTL_POWER_ON 0 229 #define URTW_LED_CTL_LINK 2 230 #define URTW_LED_CTL_TX 4 231 #define URTW_LED_PIN_GPIO0 0 232 #define URTW_LED_PIN_LED0 1 233 #define URTW_LED_PIN_LED1 2 234 #define URTW_LED_UNKNOWN 0 235 #define URTW_LED_ON 1 236 #define URTW_LED_OFF 2 237 #define URTW_LED_BLINK_NORMAL 3 238 #define URTW_LED_BLINK_SLOWLY 4 239 #define URTW_LED_POWER_ON_BLINK 5 240 #define URTW_LED_SCAN_BLINK 6 241 #define URTW_LED_NO_LINK_BLINK 7 242 #define URTW_LED_BLINK_CM3 8 243 244 /* for extra area */ 245 #define URTW_EPROM_DISABLE 0 246 #define URTW_EPROM_ENABLE 1 247 #define URTW_EPROM_DELAY 10 248 #define URTW_8187_GETREGS_REQ 5 249 #define URTW_8187_SETREGS_REQ 5 250 #define URTW_8225_RF_MAX_SENS 6 251 #define URTW_8225_RF_DEF_SENS 4 252 #define URTW_DEFAULT_RTS_RETRY 7 253 #define URTW_DEFAULT_TX_RETRY 7 254 #define URTW_DEFAULT_RTS_THRESHOLD 2342U 255 256 #define URTW_MAX_CHANNELS 15 257 258 struct urtw_tx_data { 259 struct urtw_softc *sc; 260 struct usbd_xfer *xfer; 261 uint8_t *buf; 262 struct ieee80211_node *ni; 263 }; 264 265 struct urtw_rx_data { 266 struct urtw_softc *sc; 267 struct usbd_xfer *xfer; 268 uint8_t *buf; 269 struct mbuf *m; 270 }; 271 272 /* XXX not correct.. */ 273 #define URTW_MIN_RXBUFSZ \ 274 (sizeof(struct ieee80211_frame_min)) 275 276 #define URTW_RX_DATA_LIST_COUNT 1 277 #define URTW_TX_DATA_LIST_COUNT 16 278 #define URTW_RX_MAXSIZE 0x9c4 279 #define URTW_TX_MAXSIZE 0x9c4 280 281 struct urtw_rx_radiotap_header { 282 struct ieee80211_radiotap_header wr_ihdr; 283 uint8_t wr_flags; 284 uint16_t wr_chan_freq; 285 uint16_t wr_chan_flags; 286 int8_t wr_dbm_antsignal; 287 } __packed; 288 289 #define URTW_RX_RADIOTAP_PRESENT \ 290 ((1 << IEEE80211_RADIOTAP_FLAGS) | \ 291 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 292 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL)) 293 294 struct urtw_tx_radiotap_header { 295 struct ieee80211_radiotap_header wt_ihdr; 296 uint8_t wt_flags; 297 uint8_t wt_rate; 298 uint16_t wt_chan_freq; 299 uint16_t wt_chan_flags; 300 } __packed; 301 302 #define URTW_TX_RADIOTAP_PRESENT \ 303 ((1 << IEEE80211_RADIOTAP_FLAGS) | \ 304 (1 << IEEE80211_RADIOTAP_CHANNEL)) 305 306 struct urtw_rf { 307 /* RF methods */ 308 usbd_status (*init)(struct urtw_rf *); 309 usbd_status (*set_chan)(struct urtw_rf *, int); 310 usbd_status (*set_sens)(struct urtw_rf *); 311 312 /* RF attributes */ 313 struct urtw_softc *rf_sc; 314 uint32_t max_sens; 315 uint32_t sens; 316 }; 317 318 struct urtw_softc { 319 struct device sc_dev; 320 struct ieee80211com sc_ic; 321 int (*sc_newstate)(struct ieee80211com *, 322 enum ieee80211_state, int); 323 int (*sc_init)(struct ifnet *); 324 struct urtw_rf sc_rf; 325 326 struct usb_task sc_task; 327 struct usbd_device *sc_udev; 328 struct usbd_interface *sc_iface; 329 330 enum ieee80211_state sc_state; 331 int sc_arg; 332 int sc_if_flags; 333 334 uint8_t sc_hwrev; 335 int sc_flags; 336 #define URTW_INIT_ONCE (1 << 1) 337 int sc_epromtype; 338 #define URTW_EEPROM_93C46 0 339 #define URTW_EEPROM_93C56 1 340 uint8_t sc_crcmon; 341 uint8_t sc_bssid[IEEE80211_ADDR_LEN]; 342 343 /* for LED */ 344 struct timeout sc_led_ch; 345 struct usb_task sc_ledtask; 346 uint8_t sc_psr; 347 uint8_t sc_strategy; 348 #define URTW_LED_GPIO 1 349 uint8_t sc_gpio_ledon; 350 uint8_t sc_gpio_ledinprogress; 351 uint8_t sc_gpio_ledstate; 352 uint8_t sc_gpio_ledpin; 353 uint8_t sc_gpio_blinktime; 354 uint8_t sc_gpio_blinkstate; 355 /* RX/TX */ 356 struct usbd_pipe *sc_rxpipe; 357 struct usbd_pipe *sc_txpipe_low; 358 struct usbd_pipe *sc_txpipe_normal; 359 #define URTW_PRIORITY_LOW 0 360 #define URTW_PRIORITY_NORMAL 1 361 #define URTW_DATA_TIMEOUT 10000 /* 10 sec */ 362 struct urtw_rx_data sc_rx_data[URTW_RX_DATA_LIST_COUNT]; 363 struct urtw_tx_data sc_tx_data[URTW_TX_DATA_LIST_COUNT]; 364 uint32_t sc_tx_low_queued; 365 uint32_t sc_tx_normal_queued; 366 uint32_t sc_txidx; 367 uint8_t sc_rts_retry; 368 uint8_t sc_tx_retry; 369 uint8_t sc_preamble_mode; 370 struct timeout scan_to; 371 int sc_txtimer; 372 int sc_currate; 373 /* TX power */ 374 uint8_t sc_txpwr_cck[URTW_MAX_CHANNELS]; 375 uint8_t sc_txpwr_cck_base; 376 uint8_t sc_txpwr_ofdm[URTW_MAX_CHANNELS]; 377 uint8_t sc_txpwr_ofdm_base; 378 379 #if NBPFILTER > 0 380 caddr_t sc_drvbpf; 381 382 union { 383 struct urtw_rx_radiotap_header th; 384 uint8_t pad[64]; 385 } sc_rxtapu; 386 #define sc_rxtap sc_rxtapu.th 387 int sc_rxtap_len; 388 389 union { 390 struct urtw_tx_radiotap_header th; 391 uint8_t pad[64]; 392 } sc_txtapu; 393 #define sc_txtap sc_txtapu.th 394 int sc_txtap_len; 395 #endif 396 }; 397 398