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Searched refs:UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK (Results 1 – 8 of 8) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h733 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1257 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK … macro
H A Dvcn_2_5_sh_mask.h2938 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK … macro
H A Dvcn_2_0_0_sh_mask.h2872 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3270 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK … macro
H A Dvcn_3_0_0_sh_mask.h4026 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK … macro
H A Dvcn_4_0_0_sh_mask.h4270 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4313 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK … macro