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Searched refs:VR1 (Results 1 – 3 of 3) sorted by relevance

/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonGenInsert.cpp223 bool operator() (unsigned VR1, unsigned VR2) const { in operator ()()
224 return operator[](VR1) < operator[](VR2); in operator ()()
298 bool operator() (unsigned VR1, unsigned VR2) const;
316 bool operator() (unsigned VR1, unsigned VR2) const;
327 bool RegisterCellLexCompare::operator() (unsigned VR1, unsigned VR2) const { in operator ()() argument
337 if (VR1 == VR2) in operator ()()
340 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); in operator ()()
351 return BitOrd.BaseOrd[VR1] < BitOrd.BaseOrd[VR2]; in operator ()()
355 if (VR1 == VR2) in operator ()()
357 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1); in operator ()()
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/openbsd/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp208 Register VR1 = MRI.createVirtualRegister(RC); in expandLoadACC() local
217 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
218 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); in expandLoadACC()
233 Register VR1 = MRI.createVirtualRegister(RC); in expandStoreACC() local
240 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandStoreACC()
241 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); in expandStoreACC()
266 Register VR1 = MRI.createVirtualRegister(RC); in expandCopyACC() local
275 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandCopyACC()
277 .addReg(VR1, RegState::Kill); in expandCopyACC()
H A DMipsSEISelLowering.cpp3064 Register VR1 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32() local
3065 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) in emitBPOSGE32()
3073 .addReg(VR1) in emitBPOSGE32()