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Searched refs:ValueVT (Results 1 – 17 of 17) sorted by relevance

/openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp171 if (ValueVT.isVector()) in getCopyFromParts()
180 if (ValueVT.isInteger()) { in getCopyFromParts()
252 if (PartEVT == ValueVT) in getCopyFromParts()
393 if (PartEVT == ValueVT) in getCopyFromPartsVector()
415 if (PartEVT == ValueVT) in getCopyFromPartsVector()
494 if (ValueVT.isVector()) in getCopyToParts()
508 if (PartEVT == ValueVT) { in getCopyToParts()
523 ValueVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); in getCopyToParts()
555 if (PartEVT != ValueVT) { in getCopyToParts()
666 if (PartEVT == ValueVT) { in getCopyToPartsVector()
[all …]
H A DLegalizeTypesGeneric.cpp254 EVT ValueVT = LD->getValueType(0); in ExpandRes_NormalLoad() local
255 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandRes_NormalLoad()
279 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandRes_NormalLoad()
463 EVT ValueVT = St->getValue().getValueType(); in ExpandOp_NormalStore() local
464 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandOp_NormalStore()
475 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandOp_NormalStore()
H A DFunctionLoweringInfo.cpp384 EVT ValueVT = ValueVTs[Value]; in CreateRegs() local
385 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs()
387 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT); in CreateRegs()
H A DLegalizeVectorTypes.cpp6329 EVT ValueVT = StVal.getValueType(); in WidenVecOp_MSTORE() local
6331 ValueVT.getVectorElementType(), in WidenVecOp_MSTORE()
/openbsd/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFrameLowering.cpp81 for (EVT ValueVT : ValueVTs) in getLocalForStackObject() local
82 FuncInfo->addLocal(ValueVT.getSimpleVT()); in getLocalForStackObject()
/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp153 EVT ValueVT = LD->getValueType(0); in INITIALIZE_PASS() local
154 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) { in INITIALIZE_PASS()
158 ValueVT = MVT::i32; in INITIALIZE_PASS()
162 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, in INITIALIZE_PASS()
174 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, MVT::Other, in INITIALIZE_PASS()
476 EVT ValueVT = Value.getValueType(); in SelectIndexedStore() local
523 if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) { in SelectIndexedStore()
/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp5945 MVT ValueVT = Node->getSimpleValueType(0); in Select() local
5951 if (!ValueVT.isVector() || !MaskVT.isVector()) in Select()
5954 unsigned NumElts = ValueVT.getVectorNumElements(); in Select()
5955 MVT ValueSVT = ValueVT.getVectorElementType(); in Select()
5988 assert(EVT(MaskVT) == EVT(ValueVT).changeVectorElementTypeToInteger() && in Select()
6019 SDVTList VTs = CurDAG->getVTList(ValueVT, MaskVT, MVT::Other); in Select()
6042 MVT ValueVT = Value.getSimpleValueType(); in Select() local
6047 if (!ValueVT.isVector()) in Select()
6050 unsigned NumElts = ValueVT.getVectorNumElements(); in Select()
6051 MVT ValueSVT = ValueVT.getVectorElementType(); in Select()
H A DX86ISelLowering.h1695 unsigned NumParts, MVT PartVT, EVT ValueVT,
H A DX86ISelLowering.cpp2828 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
2829 if (IsABIRegCopy && ValueVT == MVT::bf16 && PartVT == MVT::f32) { in splitValueIntoRegisterParts()
2830 unsigned ValueBits = ValueVT.getSizeInBits(); in splitValueIntoRegisterParts()
2843 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
2845 if (IsABIRegCopy && ValueVT == MVT::bf16 && PartVT == MVT::f32) { in joinRegisterPartsIntoValue()
2846 unsigned ValueBits = ValueVT.getSizeInBits(); in joinRegisterPartsIntoValue()
2852 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in joinRegisterPartsIntoValue()
/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h563 unsigned NumParts, MVT PartVT, EVT ValueVT,
H A DSystemZISelLowering.cpp1457 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
1458 assert((ValueVT != MVT::i128 || in splitValueIntoRegisterParts()
1462 if (ValueVT == MVT::i128 && NumParts == 1) { in splitValueIntoRegisterParts()
1472 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
1473 assert((ValueVT != MVT::i128 || in joinRegisterPartsIntoValue()
1477 if (ValueVT == MVT::i128 && NumParts == 1) in joinRegisterPartsIntoValue()
/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h578 unsigned NumParts, MVT PartVT, EVT ValueVT,
H A DRISCVISelLowering.cpp14110 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
14111 if (IsABIRegCopy && ValueVT == MVT::f16 && PartVT == MVT::f32) { in splitValueIntoRegisterParts()
14123 if (ValueVT.isScalableVector() && PartVT.isScalableVector()) { in splitValueIntoRegisterParts()
14125 EVT ValueEltVT = ValueVT.getVectorElementType(); in splitValueIntoRegisterParts()
14127 unsigned ValueVTBitSize = ValueVT.getSizeInBits().getKnownMinValue(); in splitValueIntoRegisterParts()
14162 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
14164 if (IsABIRegCopy && ValueVT == MVT::f16 && PartVT == MVT::f32) { in joinRegisterPartsIntoValue()
14174 if (ValueVT.isScalableVector() && PartVT.isScalableVector()) { in joinRegisterPartsIntoValue()
14177 EVT ValueEltVT = ValueVT.getVectorElementType(); in joinRegisterPartsIntoValue()
14183 EVT SameEltTypeVT = ValueVT; in joinRegisterPartsIntoValue()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMISelLowering.h901 unsigned NumParts, MVT PartVT, EVT ValueVT,
H A DARMISelLowering.cpp4426 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
4427 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) && in splitValueIntoRegisterParts()
4429 unsigned ValueBits = ValueVT.getSizeInBits(); in splitValueIntoRegisterParts()
4442 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
4444 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) && in joinRegisterPartsIntoValue()
4446 unsigned ValueBits = ValueVT.getSizeInBits(); in joinRegisterPartsIntoValue()
4452 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in joinRegisterPartsIntoValue()
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/
H A DTargetLowering.h4150 MVT PartVT, EVT ValueVT, in joinRegisterPartsIntoValue() argument
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp19327 EVT ValueVT = Value.getValueType(); in performSTORECombine() local
19341 ValueVT.isFixedLengthVector() && in performSTORECombine()
19342 ValueVT.getFixedSizeInBits() >= Subtarget->getMinSVEVectorSizeInBits() && in performSTORECombine()