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Searched refs:VecReg (Results 1 – 8 of 8) sorted by relevance

/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp686 bool HexagonMCInstrInfo::IsVecRegPair(unsigned VecReg) { in IsVecRegPair() argument
687 return (VecReg >= Hexagon::W0 && VecReg <= Hexagon::W15) || in IsVecRegPair()
688 (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15); in IsVecRegPair()
691 bool HexagonMCInstrInfo::IsReverseVecRegPair(unsigned VecReg) { in IsReverseVecRegPair() argument
692 return (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15); in IsReverseVecRegPair()
695 bool HexagonMCInstrInfo::IsVecRegSingle(unsigned VecReg) { in IsVecRegSingle() argument
696 return (VecReg >= Hexagon::V0 && VecReg <= Hexagon::V31); in IsVecRegSingle()
H A DHexagonMCInstrInfo.h366 bool IsVecRegSingle(unsigned VecReg);
367 bool IsVecRegPair(unsigned VecReg);
368 bool IsReverseVecRegPair(unsigned VecReg);
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp281 Register VecReg, unsigned LaneIdx,
3520 Register VecReg = I.getOperand(1).getReg(); in selectReduction() local
3521 LLT VecTy = MRI.getType(VecReg); in selectReduction()
3528 {VecReg, VecReg}); in selectReduction()
4108 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt() argument
4125 const RegisterBank &VecRB = *RBI.getRegBank(VecReg, MRI, TRI); in emitExtractVectorElt()
4126 const LLT &VecTy = MRI.getType(VecReg); in emitExtractVectorElt()
4135 Register InsertReg = VecReg; in emitExtractVectorElt()
4141 .addReg(VecReg, 0, ExtractSubReg); in emitExtractVectorElt()
4151 VecTy.getSizeInBits(), &AArch64::FPR128RegClass, VecReg, MIRBuilder); in emitExtractVectorElt()
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp2105 Register VecReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
2108 assert(VecReg == MI.getOperand(1).getReg()); in expandPostRAPseudo()
2112 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
2114 .addReg(VecReg, RegState::ImplicitDefine) in expandPostRAPseudo()
2115 .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0)); in expandPostRAPseudo()
2137 Register VecReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
2150 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
2152 .addReg(VecReg, RegState::ImplicitDefine) in expandPostRAPseudo()
2153 .addReg(VecReg, in expandPostRAPseudo()
2182 Register VecReg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
[all …]
H A DAMDGPURegisterBankInfo.cpp1933 Register VecReg = MI.getOperand(1).getReg(); in foldExtractEltToCmpSelect() local
1941 LLT VecTy = MRI.getType(VecReg); in foldExtractEltToCmpSelect()
1977 auto UnmergeToEltTy = B.buildUnmerge(EltTy, VecReg); in foldExtractEltToCmpSelect()
2031 Register VecReg = MI.getOperand(1).getReg(); in foldInsertEltToCmpSelect() local
2039 LLT VecTy = MRI.getType(VecReg); in foldInsertEltToCmpSelect()
2080 auto UnmergeToEltTy = B.buildUnmerge(EltTy, VecReg); in foldInsertEltToCmpSelect()
H A DAMDGPUInstructionSelector.cpp3001 Register VecReg = MI.getOperand(1).getReg(); in selectG_INSERT_VECTOR_ELT() local
3010 const RegisterBank *VecRB = RBI.getRegBank(VecReg, *MRI, TRI); in selectG_INSERT_VECTOR_ELT()
3026 if (!RBI.constrainGenericRegister(VecReg, *VecRC, *MRI) || in selectG_INSERT_VECTOR_ELT()
3052 .addReg(VecReg) in selectG_INSERT_VECTOR_ELT()
3062 .addReg(VecReg) in selectG_INSERT_VECTOR_ELT()
H A DSIISelLowering.cpp3762 unsigned VecReg, in computeIndirectRegAndOffset() argument
/openbsd/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp2476 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
2477 LLT VecTy = MRI.getType(VecReg); in widenScalar()
2501 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
2502 LLT VecTy = MRI.getType(VecReg); in widenScalar()