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Searched refs:WREG32_PLL_P (Results 1 – 5 of 5) sorted by relevance

/openbsd/sys/dev/pci/drm/radeon/
H A Dradeon_legacy_crtc.c234 WREG32_PLL_P(RADEON_PPLL_REF_DIV, in radeon_pll_write_update()
261 WREG32_PLL_P(RADEON_P2PLL_REF_DIV, in radeon_pll2_write_update()
864 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, in radeon_set_pll()
868 WREG32_PLL_P(RADEON_P2PLL_CNTL, in radeon_set_pll()
880 WREG32_PLL_P(RADEON_P2PLL_DIV_0, in radeon_set_pll()
884 WREG32_PLL_P(RADEON_P2PLL_DIV_0, in radeon_set_pll()
893 WREG32_PLL_P(RADEON_P2PLL_CNTL, in radeon_set_pll()
948 WREG32_PLL_P(RADEON_PPLL_CNTL, in radeon_set_pll()
985 WREG32_PLL_P(RADEON_PPLL_DIV_3, in radeon_set_pll()
989 WREG32_PLL_P(RADEON_PPLL_DIV_3, in radeon_set_pll()
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H A Dradeon_legacy_tv.c758 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL); in radeon_legacy_tv_mode_set()
760 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET); in radeon_legacy_tv_mode_set()
764 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET); in radeon_legacy_tv_mode_set()
769 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf); in radeon_legacy_tv_mode_set()
770 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL); in radeon_legacy_tv_mode_set()
772 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK); in radeon_legacy_tv_mode_set()
773 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP); in radeon_legacy_tv_mode_set()
H A Dradeon_legacy_encoders.c121 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); in radeon_legacy_lvds_update()
H A Dradeon.h2593 #define WREG32_PLL_P(reg, val, mask) \ macro
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu.h1237 #define WREG32_PLL_P(reg, val, mask) \ macro