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Searched refs:Writes (Results 1 – 25 of 40) sorted by relevance

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/openbsd/gnu/llvm/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp428 if (Writes.size() != Reads.size()) in tryEliminateMoveOrSwap()
435 if (Writes.empty() || Writes.size() > 2) in tryEliminateMoveOrSwap()
504 SmallVectorImpl<WriteRef> &Writes, in collectWrites() argument
521 Writes.push_back(WR); in collectWrites()
536 Writes.push_back(WR); in collectWrites()
549 if (Writes.size() > 1) { in collectWrites()
553 auto It = std::unique(Writes.begin(), Writes.end()); in collectWrites()
554 Writes.resize(std::distance(Writes.begin(), It)); in collectWrites()
571 SmallVector<WriteRef, 4> Writes; in checkRAWHazards() local
579 for (const WriteRef &WR : Writes) { in checkRAWHazards()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMScheduleA57.td67 list <SchedWriteRes> Writes = writes;
826 SchedVar<A57LMAddrPred1, A57VLDMOpsListUncond.Writes[0-1]>,
827 SchedVar<A57LMAddrPred2, A57VLDMOpsListUncond.Writes[0-3]>,
846 SchedVar<A57LMAddrPred1, A57VLDMOpsListCond.Writes[0-1]>,
847 SchedVar<A57LMAddrPred2, A57VLDMOpsListCond.Writes[0-3]>,
848 SchedVar<A57LMAddrPred3, A57VLDMOpsListCond.Writes[0-5]>,
849 SchedVar<A57LMAddrPred4, A57VLDMOpsListCond.Writes[0-7]>,
850 SchedVar<A57LMAddrPred5, A57VLDMOpsListCond.Writes[0-9]>,
851 SchedVar<A57LMAddrPred6, A57VLDMOpsListCond.Writes[0-11]>,
852 SchedVar<A57LMAddrPred7, A57VLDMOpsListCond.Writes[0-13]>,
[all …]
H A DARMScheduleA9.td1882 list <WriteSequence> Writes = writes;
2110 SchedVar<A9LMAdr1Pred, A9WriteLMOpsList.Writes[0-1]>,
2111 SchedVar<A9LMAdr2Pred, A9WriteLMOpsList.Writes[0-3]>,
2112 SchedVar<A9LMAdr3Pred, A9WriteLMOpsList.Writes[0-5]>,
2113 SchedVar<A9LMAdr4Pred, A9WriteLMOpsList.Writes[0-7]>,
2114 SchedVar<A9LMAdr5Pred, A9WriteLMOpsList.Writes[0-9]>,
2115 SchedVar<A9LMAdr6Pred, A9WriteLMOpsList.Writes[0-11]>,
2116 SchedVar<A9LMAdr7Pred, A9WriteLMOpsList.Writes[0-13]>,
2117 SchedVar<A9LMAdr8Pred, A9WriteLMOpsList.Writes[0-15]>,
2215 SchedVar<A9LMAdr1Pred, A9WriteLMfpPostRAOpsList.Writes[0-0, 8-8]>,
[all …]
H A DARMParallelDSP.cpp344 SmallVector<Instruction*, 8> Writes; in RecordMemoryOps() local
353 Writes.push_back(&I); in RecordMemoryOps()
370 for (auto *Write : Writes) { in RecordMemoryOps()
H A DARMScheduleM55.td248 // The Writes that take ResourceCycles=[2] are MVE instruction, the others VFP.
/openbsd/gnu/llvm/llvm/utils/TableGen/
H A DCodeGenSchedule.cpp880 IdxVec Writes, Reads; in collectSchedClasses() local
926 if (!SC.Writes.empty()) { in collectSchedClasses()
944 IdxVec Writes; in collectSchedClasses() local
947 Writes, Reads); in collectSchedClasses()
1036 SC.Writes = OperWrites; in addSchedClass()
1115 SC.Writes = SchedClasses[OldSCIdx].Writes; in createInstRWClass()
1262 IdxVec Writes, Reads; in inferFromItinClass() local
1284 IdxVec Writes, Reads; in inferFromInstRWs() local
1898 IdxVec Writes, Reads; in collectProcResources() local
2004 if (!SC.Writes.empty()) in checkCompleteness()
[all …]
H A DCodeGenSchedule.h128 IdxVec Writes; member
148 return ItinClassDef == IC && ArrayRef(Writes) == W && ArrayRef(Reads) == R; in isKeyEqual()
557 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
633 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
H A DSubtargetEmitter.cpp1059 IdxVec Writes = SC.Writes; in GenSchedClassTables() local
1073 Writes.clear(); in GenSchedClassTables()
1076 Writes, Reads); in GenSchedClassTables()
1079 if (Writes.empty()) { in GenSchedClassTables()
1085 Writes, Reads); in GenSchedClassTables()
1089 if (Writes.empty()) { in GenSchedClassTables()
1101 for (unsigned W : Writes) { in GenSchedClassTables()
/openbsd/gnu/llvm/llvm/lib/MC/
H A DMCInstrAnalysis.cpp22 APInt &Writes) const { in clearsSuperRegisters()
23 Writes.clearAllBits(); in clearsSuperRegisters()
/openbsd/gnu/llvm/llvm/lib/MCA/
H A DInstrBuilder.cpp322 ID.Writes.resize(TotalDefs + NumVariadicOps); in populateWrites()
339 WriteDescriptor &Write = ID.Writes[CurrentDef]; in populateWrites()
366 WriteDescriptor &Write = ID.Writes[Index]; in populateWrites()
393 WriteDescriptor &Write = ID.Writes[NumExplicitDefs + NumImplicitDefs]; in populateWrites()
417 WriteDescriptor &Write = ID.Writes[CurrentDef]; in populateWrites()
431 ID.Writes.resize(CurrentDef); in populateWrites()
729 if (D.Writes.empty()) { in createInstruction()
738 APInt WriteMask(D.Writes.size(), 0); in createInstruction()
748 for (const WriteDescriptor &WD : D.Writes) { in createInstruction()
/openbsd/gnu/llvm/llvm/lib/CodeGen/
H A DCalcSpillWeights.cpp249 bool Reads, Writes; in weightCalcHelper() local
250 std::tie(Reads, Writes) = MI->readsWritesVirtualRegister(LI.reg()); in weightCalcHelper()
251 Weight = LiveIntervals::getSpillWeight(Writes, Reads, &MBFI, *MI); in weightCalcHelper()
254 if (Writes && IsExiting && LIS.isLiveOutOfMBB(LI, MBB)) in weightCalcHelper()
H A DMLRegallocEvictAdvisor.cpp798 bool Reads, Writes; in getLIFeatureComponents() local
799 std::tie(Reads, Writes) = MI->readsWritesVirtualRegister(LI.reg()); in getLIFeatureComponents()
804 Ret.R += (Reads && !Writes) * Freq; in getLIFeatureComponents()
805 Ret.W += (!Reads && Writes) * Freq; in getLIFeatureComponents()
806 Ret.RW += (Reads && Writes) * Freq; in getLIFeatureComponents()
812 if (Writes && IsExiting && LIS->isLiveOutOfMBB(LI, MBB)) in getLIFeatureComponents()
H A DMachineInstrBundle.cpp305 RI.Writes = true; in AnalyzeVirtRegInBundle()
H A DMachinePipeliner.cpp2512 bool Reads, Writes; in orderDependence() local
2513 std::tie(Reads, Writes) = in orderDependence()
2523 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) { in orderDependence()
2532 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) { in orderDependence()
2540 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) { in orderDependence()
H A DInlineSpiller.cpp1122 if (RI.Writes) { in spillAroundUses()
1164 if (RI.Writes) in spillAroundUses()
/openbsd/gnu/llvm/llvm/lib/Transforms/Scalar/
H A DLoopDataPrefetch.cpp240 bool Writes = false; member
258 Writes = isa<StoreInst>(I); in addInstruction()
269 Writes = true; in addInstruction()
413 ConstantInt::get(I32, P.Writes), in runOnLoop()
/openbsd/gnu/llvm/llvm/include/llvm/MCA/HardwareUnits/
H A DRegisterFile.h237 SmallVectorImpl<WriteRef> &Writes,
278 bool tryEliminateMoveOrSwap(MutableArrayRef<WriteState> Writes,
/openbsd/gnu/llvm/llvm/include/llvm/MCA/
H A DInstruction.h376 void setDependentWrites(unsigned Writes) { in setDependentWrites() argument
377 DependentWrites = Writes; in setDependentWrites()
378 IsReady = !Writes; in setDependentWrites()
448 SmallVector<WriteDescriptor, 2> Writes; // Implicit writes are at the end. member
/openbsd/gnu/llvm/llvm/utils/gn/build/
H A Dwrite_vcsrevision.gni8 # Writes "$foo_REVISION" and "$foo_REPOSITORY" for each foo in names.
/openbsd/gnu/llvm/llvm/include/llvm/MC/
H A DMCInstrAnalysis.h90 APInt &Writes) const;
/openbsd/gnu/llvm/llvm/include/llvm/IR/
H A DIntrinsicsARM.td118 // Writes to the GE bits.
127 // Writes to the GE bits.
130 // Writes to the GE bits.
145 // Writes to the GE bits.
171 // Writes to the GE bits.
174 // Writes to the GE bits.
189 // Writes to the GE bits.
192 // Writes to the GE bits.
195 // Writes to the GE bits.
198 // Writes to the GE bits.
[all …]
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/
H A DMachineInstrBundle.h224 bool Writes; member
/openbsd/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp604 bool Reads, Writes; in SafeInFPUDelaySlot() local
605 std::tie(Reads, Writes) = MIInSlot.readsWritesVirtualRegister(Op.getReg()); in SafeInFPUDelaySlot()
607 if (Reads || Writes) in SafeInFPUDelaySlot()
/openbsd/gnu/llvm/llvm/include/llvm/Target/
H A DTargetSchedule.td242 list<SchedWrite> Writes = writes;
332 // to implement pipeline bypass. The Writes list may be empty to
/openbsd/gnu/usr.bin/gcc/gcc/f/
H A Dintdoc.in2322 Writes the single character @var{@1@} in stream mode to unit 6
2329 Writes the single character @var{@1@} in stream mode to unit 6
2336 Writes the single character @var{@2@} in stream mode to unit @var{@1@}
2343 Writes the single character @var{@1@} in stream mode to unit 6

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