| /openbsd/gnu/llvm/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 563 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF()
569 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF()
584 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATIMMR6()
1037 MI.addOperand( in DecodeDEXT()
1039 MI.addOperand( in DecodeDEXT()
1080 MI.addOperand( in DecodeDINS()
1082 MI.addOperand( in DecodeDINS()
2466 MI.addOperand( in DecodeBgtzGroupBranchMMR6()
2470 MI.addOperand( in DecodeBgtzGroupBranchMMR6()
2511 MI.addOperand( in DecodeBlezGroupBranchMMR6()
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| /openbsd/gnu/llvm/llvm/lib/Target/PowerPC/AsmParser/ |
| H A D | PPCAsmParser.cpp | 821 TmpInst.addOperand(Inst.getOperand(0)); in ProcessInstruction()
822 TmpInst.addOperand(Inst.getOperand(1)); in ProcessInstruction()
830 TmpInst.addOperand(Inst.getOperand(2)); in ProcessInstruction()
831 TmpInst.addOperand(Inst.getOperand(0)); in ProcessInstruction()
832 TmpInst.addOperand(Inst.getOperand(1)); in ProcessInstruction()
840 TmpInst.addOperand(Inst.getOperand(2)); in ProcessInstruction()
841 TmpInst.addOperand(Inst.getOperand(0)); in ProcessInstruction()
842 TmpInst.addOperand(Inst.getOperand(1)); in ProcessInstruction()
864 TmpInst.addOperand(Inst.getOperand(0)); in ProcessInstruction()
865 TmpInst.addOperand(Inst.getOperand(1)); in ProcessInstruction()
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| /openbsd/gnu/llvm/llvm/lib/Target/CSKY/MCTargetDesc/ |
| H A D | CSKYMCCodeEmitter.cpp | 80 .addOperand(MI.getOperand(0)) in expandJBTF()
87 .addOperand(MI.getOperand(1)) in expandJBTF()
88 .addOperand(MI.getOperand(2)); in expandJBTF()
105 .addOperand(MI.getOperand(0)) in expandNEG()
106 .addOperand(MI.getOperand(1)); in expandNEG()
111 .addOperand(MI.getOperand(0)) in expandNEG()
112 .addOperand(MI.getOperand(0)) in expandNEG()
127 .addOperand(MI.getOperand(0)) in expandRSUBI()
128 .addOperand(MI.getOperand(1)); in expandRSUBI()
133 .addOperand(MI.getOperand(0)) in expandRSUBI()
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| H A D | CSKYAsmBackend.cpp | 302 Res.addOperand(Inst.getOperand(0)); in relaxInstruction()
303 Res.addOperand(Inst.getOperand(1)); in relaxInstruction()
307 Res.addOperand(Inst.getOperand(0)); in relaxInstruction()
311 Res.addOperand(Inst.getOperand(1)); in relaxInstruction()
315 Res.addOperand(Inst.getOperand(1)); in relaxInstruction()
320 Res.addOperand(Inst.getOperand(0)); in relaxInstruction()
321 Res.addOperand(Inst.getOperand(1)); in relaxInstruction()
322 Res.addOperand(Inst.getOperand(2)); in relaxInstruction()
326 Res.addOperand(Inst.getOperand(0)); in relaxInstruction()
327 Res.addOperand(Inst.getOperand(1)); in relaxInstruction()
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| /openbsd/gnu/llvm/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2562 Inst.addOperand(MCOperand::createImm( in addRegShiftedRegOperands()
2573 Inst.addOperand(MCOperand::createImm( in addRegShiftedImmOperands()
5768 Inst.addOperand(Inst.getOperand(0)); in cvtThumbMultiply()
8739 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
8740 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
8741 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
8744 TmpInst.addOperand(Inst.getOperand(2)); in processInstruction()
8745 TmpInst.addOperand(Inst.getOperand(3)); in processInstruction()
8761 TmpInst.addOperand(Inst.getOperand(0)); in processInstruction()
8762 TmpInst.addOperand(Inst.getOperand(1)); in processInstruction()
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| /openbsd/gnu/llvm/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCompound.cpp | 216 CompoundInsn->addOperand(Rt); in getCompoundInsn()
228 CompoundInsn->addOperand(Rt); in getCompoundInsn()
229 CompoundInsn->addOperand(Rs); in getCompoundInsn()
242 CompoundInsn->addOperand(Rs); in getCompoundInsn()
243 CompoundInsn->addOperand(Rt); in getCompoundInsn()
255 CompoundInsn->addOperand(Rs); in getCompoundInsn()
256 CompoundInsn->addOperand(Rt); in getCompoundInsn()
268 CompoundInsn->addOperand(Rs); in getCompoundInsn()
269 CompoundInsn->addOperand(Rt); in getCompoundInsn()
286 CompoundInsn->addOperand(Rs); in getCompoundInsn()
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| /openbsd/gnu/llvm/llvm/lib/Target/AVR/Disassembler/ |
| H A D | AVRDisassembler.cpp | 74 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR8RegisterClass()
85 Inst.addOperand(MCOperand::createReg(Register)); in DecodeLD8RegisterClass()
141 Inst.addOperand(MCOperand::createImm(addr)); in decodeFIOARr()
157 Inst.addOperand(MCOperand::createImm(addr)); in decodeFIORdA()
165 Inst.addOperand(MCOperand::createImm(addr)); in decodeFIOBIT()
166 Inst.addOperand(MCOperand::createImm(b)); in decodeFIOBIT()
236 Inst.addOperand(MCOperand::createImm(k)); in decodeFWRdK()
263 Inst.addOperand( in decodeMemri()
286 Inst.addOperand(MCOperand::createImm(Offset)); in decodeFBRk()
356 Inst.addOperand(MCOperand::createReg(RegVal)); in decodeLoadStore()
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| /openbsd/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonAsmPrinter.cpp | 252 T.addOperand(Inst.getOperand(i)); in ScaleVectorOffset()
284 Inst.addOperand(Reg); in HexagonProcessInstruction()
286 Inst.addOperand(S16); in HexagonProcessInstruction()
338 TmpInst.addOperand(Reg); in HexagonProcessInstruction()
355 TmpInst.addOperand(Reg); in HexagonProcessInstruction()
368 MappedInst.addOperand(Ps); in HexagonProcessInstruction()
446 TmpInst.addOperand( in HexagonProcessInstruction()
482 TmpInst.addOperand( in HexagonProcessInstruction()
509 TmpInst.addOperand( in HexagonProcessInstruction()
522 TmpInst.addOperand(Rdd); in HexagonProcessInstruction()
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| /openbsd/gnu/llvm/llvm/include/llvm/MC/ |
| H A D | MCInstBuilder.h | 32 Inst.addOperand(MCOperand::createReg(Reg)); in addReg()
38 Inst.addOperand(MCOperand::createImm(Val)); in addImm()
44 Inst.addOperand(MCOperand::createSFPImm(Val)); in addSFPImm()
50 Inst.addOperand(MCOperand::createDFPImm(Val)); in addDFPImm()
56 Inst.addOperand(MCOperand::createExpr(Val)); in addExpr()
62 Inst.addOperand(MCOperand::createInst(Val)); in addInst()
67 MCInstBuilder &addOperand(const MCOperand &Op) { in addOperand() function
68 Inst.addOperand(Op); in addOperand()
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| /openbsd/gnu/llvm/llvm/lib/Target/Xtensa/Disassembler/ |
| H A D | XtensaDisassembler.cpp | 74 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeARRegisterClass()
89 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeSRRegisterClass()
145 Inst.addOperand(MCOperand::createImm( in decodeL32ROperand()
175 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUimm4Operand()
182 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUimm5Operand()
189 Inst.addOperand(MCOperand::createImm(Imm + 1)); in decodeImm1_16Operand()
197 Inst.addOperand(MCOperand::createImm(32 - Imm)); in decodeShimm1_31Operand()
207 Inst.addOperand(MCOperand::createImm(TableB4const[Imm])); in decodeB4constOperand()
218 Inst.addOperand(MCOperand::createImm(TableB4constu[Imm])); in decodeB4constuOperand()
226 Inst.addOperand(MCOperand::createImm((Imm >> 4) & 0xff)); in decodeMem8Operand()
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| /openbsd/gnu/llvm/llvm/lib/Target/PowerPC/Disassembler/ |
| H A D | PPCDisassembler.cpp | 76 Inst.addOperand(MCOperand::createImm(Offset)); in decodeDirectBrTarget()
87 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); in decodeRegisterClass()
243 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
261 Inst.addOperand(MCOperand::createImm(Imm)); in decodeImmZeroOperand()
306 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
328 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands()
344 Inst.addOperand(MCOperand::createImm(Disp)); in decodeMemRIHashOperands()
345 Inst.addOperand(MCOperand::createReg(RRegs[Base])); in decodeMemRIHashOperands()
405 Inst.addOperand(MCOperand::createImm(Disp << 3)); in decodeSPE8Operands()
421 Inst.addOperand(MCOperand::createImm(Disp << 2)); in decodeSPE4Operands()
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| /openbsd/gnu/llvm/llvm/lib/Target/VE/ |
| H A D | VEAsmPrinter.cpp | 89 SICInst.addOperand(RD); in emitSIC()
97 BSICInst.addOperand(R1); in emitBSIC()
98 BSICInst.addOperand(R2); in emitBSIC()
109 LEAInst.addOperand(RD); in emitLEAzzi()
113 LEAInst.addOperand(Imm); in emitLEAzzi()
133 LEAInst.addOperand(RD); in emitLEAzii()
136 LEAInst.addOperand(RS1); in emitLEAzii()
137 LEAInst.addOperand(Imm); in emitLEAzii()
158 Inst.addOperand(RD); in emitBinary()
159 Inst.addOperand(RS1); in emitBinary()
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| /openbsd/gnu/llvm/llvm/lib/Target/SystemZ/Disassembler/ |
| H A D | SystemZDisassembler.cpp | 87 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
173 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
266 Inst.addOperand(MCOperand::createImm(Value)); in decodePCDBLOperand()
307 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDAddr12Operand()
328 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDXAddr12Operand()
352 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDLAddr12Len4Operand()
353 Inst.addOperand(MCOperand::createImm(Length + 1)); in decodeBDLAddr12Len4Operand()
364 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDLAddr12Len8Operand()
365 Inst.addOperand(MCOperand::createImm(Length + 1)); in decodeBDLAddr12Len8Operand()
376 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDRAddr12Operand()
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| /openbsd/gnu/llvm/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 366 MI.addOperand(Imm4Op); in getInstruction()
723 Inst.addOperand( in DecodeMatrixTile()
891 Inst.addOperand(MCOperand::createImm(Imm)); in DecodeMRSSystemRegister()
901 Inst.addOperand(MCOperand::createImm(Imm)); in DecodeMSRSystemRegister()
924 Inst.addOperand(MCOperand::createImm(1)); in DecodeFMOVLaneInstruction()
1095 Inst.addOperand(Inst.getOperand(0)); in DecodeMoveImmInstruction()
1097 Inst.addOperand(MCOperand::createImm(imm)); in DecodeMoveImmInstruction()
1693 Inst.addOperand(MCOperand::createImm(imm)); in DecodeLogicalImmInstruction()
1710 Inst.addOperand(MCOperand::createImm(imm)); in DecodeModImmInstruction()
1748 Inst.addOperand(MCOperand::createImm(imm)); in DecodeModImmTiedInstruction()
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| /openbsd/gnu/llvm/llvm/lib/Target/CSKY/Disassembler/ |
| H A D | CSKYDisassembler.cpp | 114 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodeGPRRegisterClass()
186 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodesGPRRegisterClass()
231 Inst.addOperand(MCOperand::createImm(Imm << S)); in decodeUImmOperand()
240 Inst.addOperand(MCOperand::createImm(Imm + 1)); in decodeOImmOperand()
248 Inst.addOperand(MCOperand::createImm((Imm & 0x7F) << 2)); in decodeLRW16Imm8()
251 Inst.addOperand(MCOperand::createImm(V << 2)); in decodeLRW16Imm8()
263 Inst.addOperand(MCOperand::createImm(16)); in decodeJMPIXImmOperand()
265 Inst.addOperand(MCOperand::createImm(24)); in decodeJMPIXImmOperand()
267 Inst.addOperand(MCOperand::createImm(32)); in decodeJMPIXImmOperand()
269 Inst.addOperand(MCOperand::createImm(40)); in decodeJMPIXImmOperand()
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| /openbsd/gnu/llvm/llvm/lib/Target/Lanai/Disassembler/ |
| H A D | LanaiDisassembler.cpp | 127 Instr.addOperand(MCOperand::createImm(AluOp)); in PostOperandDecodeAdjust()
170 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
180 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRiMemoryValue()
182 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); in decodeRiMemoryValue()
193 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
195 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
206 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeSplsValue()
208 Inst.addOperand(MCOperand::createImm(SignExtend32<10>(Offset))); in decodeSplsValue()
225 MI.addOperand(MCOperand::createImm(Insn)); in decodeBranch()
233 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); in decodeShiftImm()
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| /openbsd/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.cpp | 38 NopInst.addOperand(MCOperand::createImm(0)); in getNop()
39 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNop()
40 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
43 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
45 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); in getNop()
46 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
47 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
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| /openbsd/gnu/llvm/llvm/lib/Target/RISCV/Disassembler/ |
| H A D | RISCVDisassembler.cpp | 72 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
83 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR16RegisterClass()
94 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32RegisterClass()
105 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32CRegisterClass()
116 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64RegisterClass()
127 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64CRegisterClass()
158 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRCRegisterClass()
169 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRPF64RegisterClass()
180 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeVRRegisterClass()
401 Inst.addOperand(Inst.getOperand(0)); in decodeRVCInstrRdRs1UImm()
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| /openbsd/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 101 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
132 MI->addOperand(*MF, MachineOperand::CreateImm(Val)); in addImm()
137 MI->addOperand(*MF, MachineOperand::CreateCImm(Val)); in addCImm()
142 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val)); in addFPImm()
153 MI->addOperand(*MF, MachineOperand::CreateFI(Idx)); in addFrameIndex()
198 MI->addOperand(*MF, MachineOperand::CreateRegMask(Mask)); in addRegMask()
225 MI->addOperand(*MF, MO); in add()
231 MI->addOperand(*MF, MO); in add()
237 MI->addOperand(*MF, MachineOperand::CreateMetadata(MD)); in addMetadata()
253 MI->addOperand(*MF, MachineOperand::CreateIntrinsicID(ID)); in addIntrinsicID()
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| /openbsd/gnu/llvm/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVAsmPrinter.cpp | 260 Inst.addOperand( in outputDebugSourceAndStrings()
271 Inst.addOperand(MCOperand::createReg(Reg)); in outputOpExtInstImports()
317 TmpInst.addOperand(MCOperand::createReg(Reg)); in outputEntryPoints()
331 Inst.addOperand(MCOperand::createImm(Cap)); in outputGlobalRequirements()
409 Inst.addOperand(MCOperand::createReg(Reg)); in outputExecutionModeFromMDNode()
443 Inst.addOperand(MCOperand::createReg(FReg)); in outputExecutionMode()
445 Inst.addOperand(MCOperand::createImm(EM)); in outputExecutionMode()
454 Inst.addOperand(MCOperand::createReg(FReg)); in outputExecutionMode()
456 Inst.addOperand(MCOperand::createImm(EM)); in outputExecutionMode()
488 Inst.addOperand(MCOperand::createReg(Reg)); in outputAnnotations()
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| /openbsd/gnu/llvm/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1692 Inst.addOperand(MCOperand::createImm(Op)); in DecodeSORegImmOperand()
2520 Inst.addOperand( in DecodeMemMultipleWritebackInstruction()
3681 Inst.addOperand(MCOperand::createImm(0)); in DecodeVLD3DupInstruction()
3815 Inst.addOperand(MCOperand::createReg(0)); in DecodeMVEModImmInstruction()
3816 Inst.addOperand(MCOperand::createImm(0)); in DecodeMVEModImmInstruction()
3842 Inst.addOperand(MCOperand::createImm(Qd)); in DecodeMVEVADCInstruction()
6154 Inst.addOperand(MCOperand::createImm(0)); in DecodeNEONComplexLane64Instruction()
6445 Inst.addOperand(MCOperand::createReg(0)); in DecodeVSCCLRM()
6713 Inst.addOperand(MCOperand::createReg(0)); in DecodeVSTRVLDR_SYSREG()
6974 Inst.addOperand(MCOperand::createReg(0)); in DecodeMVEVCMP()
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| /openbsd/gnu/llvm/llvm/lib/Target/LoongArch/Disassembler/ |
| H A D | LoongArchDisassembler.cpp | 63 Inst.addOperand(MCOperand::createReg(LoongArch::R0 + RegNo)); in DecodeGPRRegisterClass()
72 Inst.addOperand(MCOperand::createReg(LoongArch::F0 + RegNo)); in DecodeFPR32RegisterClass()
81 Inst.addOperand(MCOperand::createReg(LoongArch::F0_64 + RegNo)); in DecodeFPR64RegisterClass()
90 Inst.addOperand(MCOperand::createReg(LoongArch::FCC0 + RegNo)); in DecodeCFRRegisterClass()
99 Inst.addOperand(MCOperand::createReg(LoongArch::FCSR0 + RegNo)); in DecodeFCSRRegisterClass()
108 Inst.addOperand(MCOperand::createImm(Imm + P)); in decodeUImmOperand()
119 Inst.addOperand(MCOperand::createImm(SignExtend64<N + S>(Imm << S))); in decodeSImmOperand()
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| /openbsd/gnu/llvm/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 547 NewInst.addOperand(I); in canonicalizeImmediates()
1237 TmpInst.addOperand(Rdd); in makeCombineInst()
1238 TmpInst.addOperand(MO1); in makeCombineInst()
1239 TmpInst.addOperand(MO2); in makeCombineInst()
1349 Inst.addOperand(Reg); in processInstruction()
1351 Inst.addOperand(S27); in processInstruction()
1637 TmpInst.addOperand(Rx); in processInstruction()
1638 TmpInst.addOperand(Rx); in processInstruction()
1639 TmpInst.addOperand(Rs); in processInstruction()
1657 TmpInst.addOperand(Rx); in processInstruction()
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| /openbsd/gnu/llvm/llvm/lib/Target/ARC/Disassembler/ |
| H A D | ARCDisassembler.cpp | 140 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPR32RegisterClass()
212 Inst.addOperand(MCOperand::createImm( in DecodeSignedOperand()
224 Inst.addOperand( in DecodeFromCyclicRange()
241 Inst.addOperand(MCOperand::createImm(LImm)); in DecodeStLImmInstruction()
242 Inst.addOperand(MCOperand::createImm(0)); in DecodeStLImmInstruction()
259 Inst.addOperand(MCOperand::createImm(LImm)); in DecodeLdLImmInstruction()
260 Inst.addOperand(MCOperand::createImm(0)); in DecodeLdLImmInstruction()
316 Inst.addOperand(MCOperand::createImm(U6Field)); in DecodeCCRU6Instruction()
318 Inst.addOperand(MCOperand::createImm(CCField)); in DecodeCCRU6Instruction()
329 Inst.addOperand(MCOperand::createImm(U6)); in DecodeSOPwithRU6()
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| /openbsd/gnu/llvm/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 532 Inst.addOperand(MCOperand::createExpr(Expr)); in addExpr()
537 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
545 Inst.addOperand(MCOperand::createReg(RegNo)); in addGR32orGR64Operands()
554 Inst.addOperand(MCOperand::createReg(RegNo)); in addGR16orGR32orGR64Operands()
588 Inst.addOperand(MCOperand::createReg(Reg)); in addMaskPairOperands()
597 Inst.addOperand(MCOperand::createImm(getMemScale())); in addMemOperands()
600 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addMemOperands()
609 Inst.addOperand(MCOperand::createExpr(getMemDisp())); in addAbsMemOperands()
614 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addSrcIdxOperands()
615 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addSrcIdxOperands()
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