/openbsd/gnu/llvm/llvm/utils/TableGen/ |
H A D | RegisterBankEmitter.cpp | 72 void addRegisterClass(const CodeGenRegisterClass *RC) { in addRegisterClass() function in __anon1024e4430111::RegisterBank 292 Bank.addRegisterClass(RC); in run()
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/openbsd/gnu/llvm/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 58 addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass); in initializeHVXLowering() 59 addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass); in initializeHVXLowering() 60 addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass); in initializeHVXLowering() 61 addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass); in initializeHVXLowering() 62 addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass); in initializeHVXLowering() 63 addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass); in initializeHVXLowering() 72 addRegisterClass(MVT::v16i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering() 73 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering() 74 addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering() 82 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering() [all …]
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H A D | HexagonISelLowering.cpp | 1465 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass); in HexagonTargetLowering() 1466 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa in HexagonTargetLowering() 1469 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass); in HexagonTargetLowering() 1470 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass); in HexagonTargetLowering() 1471 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass); in HexagonTargetLowering() 1472 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering() 1473 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering() 1474 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering() 1475 addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering() 1477 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass); in HexagonTargetLowering() [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 60 addRegisterClass(MVT::i32, &WebAssembly::I32RegClass); in WebAssemblyTargetLowering() 61 addRegisterClass(MVT::i64, &WebAssembly::I64RegClass); in WebAssemblyTargetLowering() 62 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass); in WebAssemblyTargetLowering() 63 addRegisterClass(MVT::f64, &WebAssembly::F64RegClass); in WebAssemblyTargetLowering() 65 addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering() 66 addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering() 67 addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering() 68 addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering() 69 addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering() 70 addRegisterClass(MVT::v2f64, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering() [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 82 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass); in SITargetLowering() 83 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass); in SITargetLowering() 85 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass); in SITargetLowering() 86 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass); in SITargetLowering() 88 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass); in SITargetLowering() 93 addRegisterClass(MVT::f64, V64RegClass); in SITargetLowering() 94 addRegisterClass(MVT::v2f32, V64RegClass); in SITargetLowering() 96 addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass); in SITargetLowering() 99 addRegisterClass(MVT::v2i64, &AMDGPU::SGPR_128RegClass); in SITargetLowering() 100 addRegisterClass(MVT::v2f64, &AMDGPU::SGPR_128RegClass); in SITargetLowering() [all …]
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H A D | R600ISelLowering.cpp | 33 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering() 34 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering() 35 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering() 36 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering() 37 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering() 38 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
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/openbsd/gnu/llvm/llvm/lib/Target/CSKY/ |
H A D | CSKYISelLowering.cpp | 40 addRegisterClass(MVT::i32, &CSKY::GPRRegClass); in CSKYTargetLowering() 44 addRegisterClass(MVT::f32, &CSKY::sFPR32RegClass); in CSKYTargetLowering() 46 addRegisterClass(MVT::f32, &CSKY::FPR32RegClass); in CSKYTargetLowering() 49 addRegisterClass(MVT::f64, &CSKY::sFPR64RegClass); in CSKYTargetLowering() 51 addRegisterClass(MVT::f64, &CSKY::FPR64RegClass); in CSKYTargetLowering()
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/openbsd/gnu/llvm/llvm/lib/Target/VE/ |
H A D | VEISelLowering.cpp | 85 addRegisterClass(MVT::i32, &VE::I32RegClass); in initRegisterClasses() 86 addRegisterClass(MVT::i64, &VE::I64RegClass); in initRegisterClasses() 87 addRegisterClass(MVT::f32, &VE::F32RegClass); in initRegisterClasses() 88 addRegisterClass(MVT::f64, &VE::I64RegClass); in initRegisterClasses() 89 addRegisterClass(MVT::f128, &VE::F128RegClass); in initRegisterClasses() 93 addRegisterClass(VecVT, &VE::V64RegClass); in initRegisterClasses() 94 addRegisterClass(MVT::v256i1, &VE::VMRegClass); in initRegisterClasses() 95 addRegisterClass(MVT::v512i1, &VE::VM512RegClass); in initRegisterClasses()
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/openbsd/gnu/llvm/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 401 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass); in NVPTXTargetLowering() 402 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass); in NVPTXTargetLowering() 403 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass); in NVPTXTargetLowering() 404 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass); in NVPTXTargetLowering() 405 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass); in NVPTXTargetLowering() 406 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass); in NVPTXTargetLowering() 407 addRegisterClass(MVT::f16, &NVPTX::Float16RegsRegClass); in NVPTXTargetLowering() 408 addRegisterClass(MVT::v2f16, &NVPTX::Float16x2RegsRegClass); in NVPTXTargetLowering() 409 addRegisterClass(MVT::bf16, &NVPTX::Float16RegsRegClass); in NVPTXTargetLowering() 410 addRegisterClass(MVT::v2bf16, &NVPTX::Float16x2RegsRegClass); in NVPTXTargetLowering()
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/openbsd/gnu/llvm/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 68 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); in MipsSETargetLowering() 71 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); in MipsSETargetLowering() 89 addRegisterClass(VecTy, &Mips::DSPRRegClass); in MipsSETargetLowering() 124 addRegisterClass(MVT::f16, &Mips::MSA128HRegClass); in MipsSETargetLowering() 165 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); in MipsSETargetLowering() 170 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); in MipsSETargetLowering() 172 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); in MipsSETargetLowering() 312 addRegisterClass(Ty, RC); in addMSAIntType() 366 addRegisterClass(Ty, RC); in addMSAFloatType()
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H A D | Mips16ISelLowering.cpp | 125 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); in Mips16TargetLowering()
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/openbsd/gnu/llvm/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 61 addRegisterClass(MVT::i64, &BPF::GPRRegClass); in BPFTargetLowering() 63 addRegisterClass(MVT::i32, &BPF::GPR32RegClass); in BPFTargetLowering()
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/openbsd/gnu/llvm/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 90 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass); in SystemZTargetLowering() 92 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass); in SystemZTargetLowering() 93 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass); in SystemZTargetLowering() 96 addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass); in SystemZTargetLowering() 97 addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass); in SystemZTargetLowering() 99 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass); in SystemZTargetLowering() 100 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass); in SystemZTargetLowering() 103 addRegisterClass(MVT::f128, &SystemZ::VR128BitRegClass); in SystemZTargetLowering() 105 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass); in SystemZTargetLowering() 108 addRegisterClass(MVT::v16i8, &SystemZ::VR128BitRegClass); in SystemZTargetLowering() [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1555 addRegisterClass(MVT::i32, &SP::IntRegsRegClass); in SparcTargetLowering() 1557 addRegisterClass(MVT::f32, &SP::FPRegsRegClass); in SparcTargetLowering() 1558 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass); in SparcTargetLowering() 1559 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass); in SparcTargetLowering() 1562 addRegisterClass(MVT::i64, &SP::I64RegsRegClass); in SparcTargetLowering() 1566 addRegisterClass(MVT::v2i32, &SP::IntPairRegClass); in SparcTargetLowering()
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/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 167 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering() 170 addRegisterClass(MVT::f32, &PPC::GPRCRegClass); in PPCTargetLowering() 173 addRegisterClass(MVT::f64, &PPC::SPERCRegClass); in PPCTargetLowering() 175 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering() 176 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering() 295 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass); in PPCTargetLowering() 729 addRegisterClass(MVT::i64, &PPC::G8RCRegClass); in PPCTargetLowering() 926 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); in PPCTargetLowering() 927 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass); in PPCTargetLowering() 928 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass); in PPCTargetLowering() [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 326 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass); in AArch64TargetLowering() 327 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass); in AArch64TargetLowering() 336 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass); in AArch64TargetLowering() 337 addRegisterClass(MVT::bf16, &AArch64::FPR16RegClass); in AArch64TargetLowering() 338 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass); in AArch64TargetLowering() 339 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass); in AArch64TargetLowering() 344 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass); in AArch64TargetLowering() 398 addRegisterClass(VT, &AArch64::ZPRRegClass); in AArch64TargetLowering() 402 addRegisterClass(VT, &AArch64::ZPRRegClass); in AArch64TargetLowering() 1936 addRegisterClass(VT, &AArch64::FPR64RegClass); in addDRTypeForNEON() [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 49 addRegisterClass(MVT::i8, &MSP430::GR8RegClass); in MSP430TargetLowering() 50 addRegisterClass(MVT::i16, &MSP430::GR16RegClass); in MSP430TargetLowering()
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/openbsd/gnu/llvm/llvm/lib/Target/ARC/ |
H A D | ARCISelLowering.cpp | 100 addRegisterClass(MVT::i32, &ARC::GPR32RegClass); in ARCTargetLowering()
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/openbsd/gnu/llvm/llvm/lib/Target/LoongArch/ |
H A D | LoongArchISelLowering.cpp | 48 addRegisterClass(GRLenVT, &LoongArch::GPRRegClass); in LoongArchTargetLowering() 50 addRegisterClass(MVT::f32, &LoongArch::FPR32RegClass); in LoongArchTargetLowering() 52 addRegisterClass(MVT::f64, &LoongArch::FPR64RegClass); in LoongArchTargetLowering()
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/openbsd/gnu/llvm/llvm/lib/Target/M68k/ |
H A D | M68kISelLowering.cpp | 58 addRegisterClass(MVT::i8, &M68k::DR8RegClass); in M68kTargetLowering() 59 addRegisterClass(MVT::i16, &M68k::XR16RegClass); in M68kTargetLowering() 60 addRegisterClass(MVT::i32, &M68k::XR32RegClass); in M68kTargetLowering()
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/openbsd/gnu/llvm/llvm/docs/ |
H A D | WritingAnLLVMBackend.rst | 1381 ``addRegisterClass`` method to specify which types are supported and which 1390 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 1391 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 1392 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
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/openbsd/gnu/llvm/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 178 addRegisterClass(MVT::i8, &X86::GR8RegClass); in X86TargetLowering() 179 addRegisterClass(MVT::i16, &X86::GR16RegClass); in X86TargetLowering() 180 addRegisterClass(MVT::i32, &X86::GR32RegClass); in X86TargetLowering() 182 addRegisterClass(MVT::i64, &X86::GR64RegClass); in X86TargetLowering() 680 addRegisterClass(MVT::f32, &X86::FR32RegClass); in X86TargetLowering() 682 addRegisterClass(MVT::f64, &X86::RFP64RegClass); in X86TargetLowering() 712 addRegisterClass(MVT::f64, &X86::RFP64RegClass); in X86TargetLowering() 713 addRegisterClass(MVT::f32, &X86::RFP32RegClass); in X86TargetLowering() 770 addRegisterClass(MVT::f80, &X86::RFP80RegClass); in X86TargetLowering() 1586 addRegisterClass(MVT::v1i1, &X86::VK1RegClass); in X86TargetLowering() [all …]
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/openbsd/gnu/llvm/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 40 addRegisterClass(MVT::i8, &AVR::GPR8RegClass); in AVRTargetLowering() 41 addRegisterClass(MVT::i16, &AVR::DREGSRegClass); in AVRTargetLowering()
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/openbsd/gnu/llvm/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 77 addRegisterClass(MVT::i32, &Lanai::GPRRegClass); in LanaiTargetLowering()
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/openbsd/gnu/llvm/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 218 addRegisterClass(VT, &ARM::DPRRegClass); in addDRTypeForNEON() 223 addRegisterClass(VT, &ARM::DPairRegClass); in addQRTypeForNEON() 251 addRegisterClass(VT, &ARM::MQPRRegClass); in addMVEVectorTypes() 326 addRegisterClass(VT, &ARM::MQPRRegClass); in addMVEVectorTypes() 394 addRegisterClass(VT, &ARM::MQPRRegClass); in addMVEVectorTypes() 440 addRegisterClass(VT, &ARM::VCCRRegClass); in addMVEVectorTypes() 767 addRegisterClass(MVT::i32, &ARM::tGPRRegClass); in ARMTargetLowering() 769 addRegisterClass(MVT::i32, &ARM::GPRRegClass); in ARMTargetLowering() 773 addRegisterClass(MVT::f32, &ARM::SPRRegClass); in ARMTargetLowering() 774 addRegisterClass(MVT::f64, &ARM::DPRRegClass); in ARMTargetLowering() [all …]
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