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/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64SystemOperands.td255 def : PRFM<"pld", 0b00, "slc", 0b11, "keep", 0b0>;
256 def : PRFM<"pld", 0b00, "slc", 0b11, "strm", 0b1>;
265 def : PRFM<"pli", 0b01, "slc", 0b11, "keep", 0b0>;
266 def : PRFM<"pli", 0b01, "slc", 0b11, "strm", 0b1>;
275 def : PRFM<"pst", 0b10, "slc", 0b11, "keep", 0b0>;
276 def : PRFM<"pst", 0b10, "slc", 0b11, "strm", 0b1>;
1365 0b11, 0b000, 0b0110, 0b1000, 0b000>{
1371 0b11, 0b000, 0b0110, 0b1000, 0b001>{
1381 def : RWSysReg<"PAN", 0b11, 0b000, 0b0100, 0b0010, 0b011>;
1428 def : RWSysReg<"UAO", 0b11, 0b000, 0b0100, 0b0010, 0b100>;
[all …]
H A DAArch64SMEInstrInfo.td357 defm UMLSL_MZZI : sme2_mla_long_array_index<"umlsl", 0b11, 0b11, nxv8i16, int_aarch64_sme_u…
358 defm UMLSL_VG2_M2ZZI : sme2_int_mla_long_array_vg2_index<"umlsl", 0b11, int_aarch64_sme_umlsl_lane…
359 defm UMLSL_VG4_M4ZZI : sme2_int_mla_long_array_vg4_index<"umlsl", 0b11, int_aarch64_sme_umlsl_lane…
361 defm UMLSL_VG2_M2ZZ : sme2_int_mla_long_array_vg2_single<"umlsl", 0b11, int_aarch64_sme_umlsl_sing…
363 defm UMLSL_VG2_M2Z2Z : sme2_int_mla_long_array_vg2_multi<"umlsl", 0b11, int_aarch64_sme_umlsl_vg2x…
364 defm UMLSL_VG4_M4Z4Z : sme2_int_mla_long_array_vg4_multi<"umlsl", 0b11, int_aarch64_sme_umlsl_vg2x…
769 def UMLSLL_MZZI_HtoD : sme2_mla_ll_array_index_64b<"umlsll", 0b11>;
770 defm UMLSLL_VG2_M2ZZI_HtoD : sme2_mla_ll_array_vg2_index_64b<"umlsll", 0b11>;
771 defm UMLSLL_VG4_M4ZZI_HtoD : sme2_mla_ll_array_vg4_index_64b<"umlsll", 0b11>;
857 defm BFMLS_VG2_M2ZZI : sme2p1_multi_vec_array_vg2_index_16b<"bfmls", 0b11>;
[all …]
H A DAArch64SVEInstrInfo.td438 defm BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic", AArch64bic>;
871 defm BRKPBS_PPzPP : sve_int_brkp<0b11, "brkpbs", null_frag>;
937 defm LD1D_Q_IMM : sve_mem_128b_cld_si<0b11, "ld1d">;
956 defm LD1RD_IMM : sve_mem_ld_dup<0b11, 0b11, "ld1rd", Z_d, ZPR64, uimm6s8>;
1294 defm LDNT1D_ZRI : sve_mem_cldnt_si<0b11, "ldnt1d", Z_d, ZPR64>;
1315 defm ST1D_IMM : sve_mem_cst_si<0b11, 0b11, "st1d", Z_d, ZPR64>;
1482 defm ST4D_IMM : sve_mem_est_si<0b11, 0b11, ZZZZ_d, "st4d", simm4s4>;
1501 def ST4D : sve_mem_est_ss<0b11, 0b11, ZZZZ_d, "st4d", GPR64NoXZRshifted64>;
1511 defm STNT1D_ZRI : sve_mem_cstnt_si<0b11, "stnt1d", Z_d, ZPR64>;
1529 defm PRFD_PRI : sve_mem_prfm_si<0b11, "prfd">;
[all …]
H A DSVEInstrFormats.td686 let Inst{15-14} = 0b11;
1022 let Inst{21-20} = 0b11;
1645 let Inst{15-14} = 0b11;
2879 def _D : sve_int_bin_pred_arit_log<0b11, 0b11, opc, asm, ZPR64>,
2984 let Inst{15-14} = 0b11;
3432 let Inst{15-14} = 0b11;
3965 let Inst{15-14} = 0b11;
4456 let Inst{15-14} = 0b11;
6733 def _D : sve_int_perm_rev<0b11, 0b11, asm, ZPR64>;
8009 def _D : sve_int_reduce<0b11, 0b11, opc, asm, ZPR64, FPR64asZPR>;
[all …]
H A DSMEInstrFormats.td492 def _D : sme_mem_ld_ss_inst<0b0, 0b11, mnemonic # "d",
500 def _Q : sme_mem_ld_ss_inst<0b1, 0b11, mnemonic # "q",
630 def _D : sme_mem_st_ss_inst<0b0, 0b11, mnemonic # "d",
638 def _Q : sme_mem_st_ss_inst<0b1, 0b11, mnemonic # "q",
1222 def _D : sve2_clamp<asm, 0b11, U, ZPR64>;
2026 let Inst{21-20} = 0b11;
3063 def _D : sme2_mova_vec_to_tile_vg2_multi_base<0b11, v,
4009 def _D : sme2_sel_vector_vg2<0b11, ZZ_d_mul_r, mnemonic>;
4025 def _D : sme2_sel_vector_vg4<0b11, ZZZZ_d_mul_r, mnemonic>;
4296 def _D : sme2p1_movaz_tile_to_vec_base<0b11, 0b0, v, ZPR64,
[all …]
H A DAArch64InstrInfo.td1033 let CRm{1-0} = 0b11;
1153 def RAX1 : CryptoRRR_2D<0b0,0b11, "rax1">;
1259 def LDAPRX : RCPCLoad<0b11, "ldapr", GPR64>;
1591 defm MOVK : InsertImmediate<0b11, "movk">;
1868 defm RORV : Shift<0b11, "ror", rotr>;
2134 defm STZ2G : MemTagStore<0b11, "stz2g">;
2217 defm BICS : LogicalRegS<0b11, 1, "bics",
2759 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
3082 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
3124 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
[all …]
H A DAArch64InstrFormats.td2766 let Inst{14-13} = 0b11;
2840 let Inst{14-13} = 0b11;
4233 let Inst{11-10} = 0b11;
5482 let Inst{11-10} = 0b11;
5759 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,0b11}, {0b11,opc}, V128,
5782 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,0b11}, {0b11,opc}, V128,
5808 def v2f64 : BaseSIMDThreeSameVectorTied<1, U, {S,0b11}, {0b11,opc}, V128,
7099 def NAME#64 : BaseSIMDThreeScalar<U, {S,0b11}, {0b11,opc}, FPR64, asm,
7117 def NAME#64 : BaseSIMDThreeScalar<U, {S,0b11}, {0b11,opc}, FPR64, asm,
11688 def TN : MOPSMemoryCopy<opcode, 0b11, 0b11, asm # "tn">;
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMInstrVFP.td588 def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
593 def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
602 def VCMPEH : AHuI<0b11101, 0b11, 0b0100, 0b11, 0,
631 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
636 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
645 def VABSH : AHuI<0b11101, 0b11, 0b0000, 0b11, 0,
651 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
659 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
1022 def H : AHuI<0b11101, 0b11, 0b0110, 0b11, 0,
1031 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,
[all …]
H A DARMInstrNEON.td5844 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
5847 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
5850 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
5853 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
5856 def VRECPEhd : N2VDInt<0b11, 0b11, 0b01, 0b11, 0b01010, 0,
5860 def VRECPEhq : N2VQInt<0b11, 0b11, 0b01, 0b11, 0b01010, 0,
5882 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
5885 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
5888 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
5891 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
[all …]
H A DARMInstrMVE.td412 let Inst{27-26} = 0b11;
839 let Inst{19-18} = 0b11;
1417 let Inst{10-9} = 0b11;
1429 let Inst{25-24} = 0b11;
1461 let Inst{25-24} = 0b11;
1539 let Inst{21-20} = 0b11;
2461 let Inst{21-20} = 0b11;
2502 let Inst{21-20} = 0b11;
2507 let Inst{9-8} = 0b11;
2672 let Inst{21-20} = 0b11;
[all …]
H A DARMInstrCDE.td61 let Inst{27-26} = 0b11;
342 let Inst{21-20} = 0b11;
364 let Inst{21-20} = 0b11;
/openbsd/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td430 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
474 class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>;
522 class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>;
543 class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>;
550 class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>;
851 class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>;
1016 class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>;
1036 class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>;
1056 class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>;
1076 class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>;
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/M68k/
H A DM68kInstrFormats.td217 def MxEncEAf_0: MxEncEA<MxBeadReg<0>, MxBead2Bits<0b11>, MxBead1Bit<0>>;
229 def MxEncEAf_1: MxEncEA<MxBeadReg<1>, MxBead2Bits<0b11>, MxBead1Bit<0>>;
238 def MxEncEAf_2: MxEncEA<MxBeadReg<2>, MxBead2Bits<0b11>, MxBead1Bit<0>>;
240 def MxEncEAb : MxEncEA<MxBead3Bits<0b001>, MxBead2Bits<0b11>, MxBead1Bit<1>>;
241 def MxEncEAq : MxEncEA<MxBead3Bits<0b010>, MxBead2Bits<0b11>, MxBead1Bit<1>>;
242 def MxEncEAk : MxEncEA<MxBead3Bits<0b011>, MxBead2Bits<0b11>, MxBead1Bit<1>>;
243 def MxEncEAi : MxEncEA<MxBead3Bits<0b100>, MxBead2Bits<0b11>, MxBead1Bit<1>>;
258 !eq(scale, 8) : 0b11
462 def MxEncSize64 : MxEncSize<0b11>;
472 def MxNewEncSize64 : MxNewEncSize<0b11>;
H A DM68kInstrControl.td99 let Inst = (descend 0b0101, !cast<MxEncCondOp>("MxCC"#CC).Value, 0b11,
109 (descend 0b0101, !cast<MxEncCondOp>("MxCC"#CC).Value, 0b11, DST_ENC.EA),
136 (descend 0b0100, 0b1110, 0b11, DST_ENC.EA),
H A DM68kInstrShiftRotate.td36 defvar MxROOP_RO = 0b11;
/openbsd/regress/lib/libcrypto/x509/bettertls/certificates/
H A D2687.crt14 zIaUKfmLmSN6+38ksHx8yzn8DEwf6P0rYaTIPQ8ClqnhQOw2XAfzxcsRO+b11+/8
/openbsd/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo16Instr.td66 def SUBC16 : R16_XZ_BINOP_C<0b1000, 0b11, "subc16">;
84 def ROTL16 : R16_XZ_BINOP<0b1100, 0b11, "rotl16", BinOpFrag<(rotl node:$LHS, (and node:$RHS, 0x1f))…
91 def SEXTH16 : R16_XZ_UNOP<0b1101, 0b11, "sexth16">;
116 def SUBI16XZ : I16_XZ_IMM3<0b11, "subi16", sub>;
183 let Inst{1,0} = 0b11;
194 let Inst{1,0} = 0b11;
285 def REVH16 : R16_XZ_UNOP<0b1110, 0b11, "revh16">;
339 let Inst{1,0} = 0b11;
H A DCSKYInstrFormatsF2.td75 def _RNI : F2_XZ_P<datatype, {sop, 0b11}, op#".rni", [], outs, ins>;
/openbsd/usr.bin/file/magdir/
H A Dfsav28 #>>>>10 byte 10 \b11-
/openbsd/lib/libcrypto/curve25519/
H A Dcurve25519.c4163 int64_t b11 = (load_4(b + 28) >> 7); in sc_muladd() local
4239 s11 = c11 + a0 * b11 + a1 * b10 + a2 * b9 + a3 * b8 + a4 * b7 + a5 * b6 + in sc_muladd()
4241 s12 = a1 * b11 + a2 * b10 + a3 * b9 + a4 * b8 + a5 * b7 + a6 * b6 + a7 * b5 + in sc_muladd()
4243 s13 = a2 * b11 + a3 * b10 + a4 * b9 + a5 * b8 + a6 * b7 + a7 * b6 + a8 * b5 + in sc_muladd()
4245 s14 = a3 * b11 + a4 * b10 + a5 * b9 + a6 * b8 + a7 * b7 + a8 * b6 + a9 * b5 + in sc_muladd()
4250 s17 = a6 * b11 + a7 * b10 + a8 * b9 + a9 * b8 + a10 * b7 + a11 * b6; in sc_muladd()
4251 s18 = a7 * b11 + a8 * b10 + a9 * b9 + a10 * b8 + a11 * b7; in sc_muladd()
4252 s19 = a8 * b11 + a9 * b10 + a10 * b9 + a11 * b8; in sc_muladd()
4253 s20 = a9 * b11 + a10 * b10 + a11 * b9; in sc_muladd()
4254 s21 = a10 * b11 + a11 * b10; in sc_muladd()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsV.td31 def MOPLDIndexedOrder : RISCVMOP<0b11>;
36 def MOPSTIndexedOrder : RISCVMOP<0b11>;
/openbsd/gnu/llvm/llvm/lib/Target/ARC/
H A DARCInstrFormats.td300 let Inst{23-22} = 0b11;
344 let Inst{23-22} = 0b11;
369 let Inst{23-22} = 0b11;
1033 F16_BCC<0b11, (ins btargetS7:$s),
/openbsd/gnu/llvm/llvm/include/llvm/ExecutionEngine/JITLink/
H A Daarch64.h335 uint32_t ImplicitShift = (Instr >> 21) & 0b11; in getMoveWide16Shift()
/openbsd/gnu/llvm/llvm/lib/Target/AVR/
H A DAVRInstrInfo.td387 : FRdRr<0b0000, 0b11,
422 : FRdRr<0b0001, 0b11,
660 def MULRdRr : FRdRr<0b1001, 0b11, (outs),
697 def FMULSU : FFMULRdRr<0b11, (outs),
1108 def SBRSRrB : FRdB<0b11, (outs),
1120 def SBISAb : FIOBIT<0b11, (outs),
1247 def MOVRdRr : FRdRr<0b0010, 0b11,
/openbsd/gnu/llvm/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
H A DSVals.h80 enum { BaseBits = 2, BaseMask = 0b11 };

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