Home
last modified time | relevance | path

Searched refs:cfgBIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL (Results 1 – 2 of 2) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_7_0_offset.h2632 #define cfgBIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL … macro
H A Dnbio_7_2_0_offset.h3023 #define cfgBIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL … macro