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Searched refs:cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP (Results 1 – 3 of 3) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_offset.h1262 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP … macro
H A Dnbio_2_3_offset.h1768 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP … macro
H A Dnbio_4_3_0_offset.h3488 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP … macro