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Searched refs:cfgBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL (Results 1 – 2 of 2) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_offset.h241 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL macro
H A Dnbio_4_3_0_offset.h2855 #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL macro