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Searched refs:cfgcr2 (Results 1 – 3 of 3) sorted by relevance

/openbsd/sys/dev/pci/drm/i915/display/
H A Dintel_dpll_mgr.c1238 i915_reg_t ctl, cfgcr1, cfgcr2; member
1252 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
1258 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
1264 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
1288 intel_de_write(dev_priv, regs[id].cfgcr2, pll->state.hw_state.cfgcr2); in skl_ddi_pll_enable()
1348 hw_state->cfgcr2 = intel_de_read(dev_priv, regs[id].cfgcr2); in skl_ddi_pll_get_hw_state()
1637 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK; in skl_ddi_wrpll_get_freq()
1638 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK; in skl_ddi_wrpll_get_freq()
1705 u32 ctrl1, cfgcr1, cfgcr2; in skl_ddi_hdmi_pll_dividers() local
1733 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; in skl_ddi_hdmi_pll_dividers()
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H A Dintel_dpll_mgr.h205 u32 cfgcr1, cfgcr2; member
H A Dintel_display.c5324 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); in intel_pipe_config_compare()