Home
last modified time | relevance | path

Searched refs:cycles (Results 1 – 25 of 244) sorted by relevance

12345678910

/openbsd/gnu/usr.bin/binutils/opcodes/
H A Dmsp430-dis.c80 int cycles = 0; local
112 &cycles);
263 *cycles = 1;
325 *cycles = 1;
329 *cycles = 1;
349 *cycles = 1;
377 *cycles = 4;
475 *cycles = 1;
557 *cycles = 2;
563 *cycles = 3;
[all …]
/openbsd/gnu/usr.bin/binutils-2.17/opcodes/
H A Dmsp430-dis.c57 int *cycles) in msp430_nooperands() argument
118 *cycles = 1; in msp430_singleoperand()
179 *cycles = 1; in msp430_singleoperand()
183 *cycles = 1; in msp430_singleoperand()
203 *cycles = 1; in msp430_singleoperand()
231 *cycles = 4; in msp430_singleoperand()
330 *cycles = 1; in msp430_doubleoperand()
412 *cycles = 2; in msp430_doubleoperand()
418 *cycles = 3; in msp430_doubleoperand()
426 *cycles = 1; in msp430_doubleoperand()
[all …]
/openbsd/sys/dev/pci/drm/i915/gt/
H A Dselftest_gt_pm.c56 u32 cycles[5]; in measure_clocks() local
61 cycles[i] = -read_timestamp(engine); in measure_clocks()
66 cycles[i] += read_timestamp(engine); in measure_clocks()
72 sort(cycles, 5, sizeof(*cycles), cmp_u32, NULL); in measure_clocks()
73 *out_cycles = (cycles[1] + 2 * cycles[2] + cycles[3]) / 4; in measure_clocks()
98 u32 cycles; in live_gt_clocks() local
106 measure_clocks(engine, &cycles, &dt); in live_gt_clocks()
108 time = intel_gt_clock_interval_to_ns(engine->gt, cycles); in live_gt_clocks()
112 engine->name, cycles, time, dt, expected, in live_gt_clocks()
122 if (9 * expected < 8 * cycles || 8 * expected > 9 * cycles) { in live_gt_clocks()
/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCScheduleP10.td120 // A BR pipeline may take 2 cycles to complete.
125 // A CY pipeline may take 7 cycles to complete.
268 // A DX pipeline may take 5 cycles to complete.
273 // A F2 pipeline may take 4 cycles to complete.
287 // A LD pipeline may take 6 cycles to complete.
292 // A MF pipeline may take 13 cycles to complete.
302 // A MM pipeline may take 10 cycles to complete.
307 // A MU pipeline may take 5 cycles to complete.
312 // A PM pipeline may take 4 cycles to complete.
317 // A ST pipeline may take 3 cycles to complete.
[all …]
/openbsd/gnu/llvm/lldb/scripts/
H A Danalyze-project-deps.py85 def is_existing_cycle(path, cycles): argument
106 if is_existing_cycle(cur_path, cycles):
123 cycles.append(cycle)
130 cycles = [] variable
150 def iter_cycles(cycles): argument
152 for cycle in cycles:
166 expand(path_queue, path_lens, cycles, src_map)
168 average = sum([len(x)+1 for x in cycles]) / len(cycles)
171 counted = list(iter_cycles(cycles))
181 for cycle in cycles:
[all …]
/openbsd/sys/dev/fdt/
H A Dsxipwm.c146 uint64_t rate, cycles, act_cycles; in sxipwm_get_state() local
166 cycles = ((ch_period >> PWM_CH0_CYCLES_SHIFT) & in sxipwm_get_state()
172 ps->ps_period = (NS_PER_S * cycles) / rate; in sxipwm_get_state()
185 uint64_t rate, cycles, act_cycles; in sxipwm_set_state() local
195 cycles = (rate * ps->ps_period) / NS_PER_S; in sxipwm_set_state()
196 if ((cycles - 1) < PWM_CH0_CYCLES_MAX) { in sxipwm_set_state()
205 cycles = (rate * ps->ps_period) / NS_PER_S; in sxipwm_set_state()
207 if (cycles < 1 || act_cycles > cycles) in sxipwm_set_state()
210 KASSERT(cycles - 1 <= PWM_CH0_CYCLES_MAX); in sxipwm_set_state()
228 reg = ((cycles - 1) << PWM_CH0_CYCLES_SHIFT) | in sxipwm_set_state()
H A Drkpwm.c129 uint64_t rate, cycles, act_cycles; in rkpwm_get_state() local
135 cycles = HREAD4(sc, PWM_V2_PERIOD); in rkpwm_get_state()
139 ps->ps_period = (NS_PER_S * cycles) / rate; in rkpwm_get_state()
152 uint64_t rate, cycles, act_cycles; in rkpwm_set_state() local
163 cycles = (rate * ps->ps_period) / NS_PER_S; in rkpwm_set_state()
165 if (cycles < 1 || act_cycles > cycles) in rkpwm_set_state()
168 HWRITE4(sc, PWM_V2_PERIOD, cycles); in rkpwm_set_state()
/openbsd/gnu/gcc/gcc/config/mips/
H A D24k.md169 ;; load->load base: 3 cycles
170 ;; load->store base: 3 cycles
171 ;; load->prefetch: 3 cycles
177 ;; arith->load base: 2 cycles
178 ;; arith->store base: 2 cycles
179 ;; arith->prefetch: 2 cycles
185 ;; mul3->l/s base : 6 cycles
186 ;; mul3->prefetch : 6 cycles
201 ;; cop->l/s base : 4 cycles
206 ;; multi->l/s base : 2 cycles
[all …]
H A Dsb1.md26 ;; for 3 cycles. When an FP insn is issued, no MDMX insn can be issued for
27 ;; 5 cycles. This is currently not handled because there is no MDMX insn
295 ;; mt{hi,lo} to mul/div is 4 cycles.
302 ;; mt{hi,lo} to mf{hi,lo} is 3 cycles.
306 ;; multiply latency to an EX operation is 3 cycles.
317 ;; muldi to mfhi is 4 cycles.
326 ;; muldi to mflo is 3 cycles.
330 ;; mul latency is 7 cycles if the result is used by any LS insn.
347 ;; a time, but the first/last 4 cycles can overlap.
395 ;; ??? Blocks issue of another non-madd/msub after 4 cycles.
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMScheduleA9.td81 // No operand cycles
468 // Extra latency cycles since wbck is 2 cycles
477 // Extra latency cycles since wbck is 2 cycles
487 // Extra latency cycles since wbck is 4 cycles
496 // Extra latency cycles since wbck is 4 cycles
880 // Extra latency cycles since wbck is 7 cycles
908 // Extra latency cycles since wbck is 7 cycles
1279 // Extra latency cycles since wbck is 6 cycles
1288 // Extra latency cycles since wbck is 6 cycles
1297 // Extra latency cycles since wbck is 6 cycles
[all …]
/openbsd/sys/arch/i386/i386/
H A Dlapic.c261 uint32_t cycles; in lapic_timer_rearm() local
265 cycles = (nsecs * lapic_timer_nsec_cycle_ratio) >> 32; in lapic_timer_rearm()
266 if (cycles == 0) in lapic_timer_rearm()
267 cycles = 1; in lapic_timer_rearm()
268 lapic_timer_oneshot(0, cycles); in lapic_timer_rearm()
289 lapic_timer_start(uint32_t mode, uint32_t mask, uint32_t cycles) in lapic_timer_start() argument
293 i82489_writereg(LAPIC_ICR_TIMER, cycles); in lapic_timer_start()
297 lapic_timer_oneshot(uint32_t mask, uint32_t cycles) in lapic_timer_oneshot() argument
299 lapic_timer_start(LAPIC_LVTT_TM_ONESHOT, mask, cycles); in lapic_timer_oneshot()
303 lapic_timer_periodic(uint32_t mask, uint32_t cycles) in lapic_timer_periodic() argument
[all …]
/openbsd/gnu/gcc/gcc/config/sparc/
H A Dniagara.md79 * FPADD{s,d}: 26 cycles
80 * FPSUB{s,d}: 26 cycles
81 * FABSD: 26 cycles
82 * F{s,d}TO{s,d}: 26 cycles
83 * F{s,d}TO{i,x}: 26 cycles
84 * FSMULD: 29 cycles
112 * FPADD{16,32}: 10 cycles
113 * FPSUB{16,32}: 10 cycles
114 * FALIGNDATA: 10 cycles
/openbsd/sys/arch/riscv64/dev/
H A Dsxitimer.c156 uint32_t cycles; in sxitimer_rearm() local
160 cycles = (nsecs * sc->sc_nsec_cycle_ratio) >> 32; in sxitimer_rearm()
161 if (cycles > UINT32_MAX) in sxitimer_rearm()
162 cycles = UINT32_MAX; in sxitimer_rearm()
163 if (cycles < 1) in sxitimer_rearm()
164 cycles = 1; in sxitimer_rearm()
165 HWRITE4(sc, TMR0_INTV_VALUE, cycles); in sxitimer_rearm()
/openbsd/sys/arch/powerpc64/powerpc64/
H A Dclock.c59 uint32_t cycles; in dec_rearm() local
63 cycles = (nsecs * dec_nsec_cycle_ratio) >> 32; in dec_rearm()
64 if (cycles > UINT32_MAX >> 1) in dec_rearm()
65 cycles = UINT32_MAX >> 1; in dec_rearm()
66 mtdec(cycles); in dec_rearm()
/openbsd/sys/arch/arm64/dev/
H A Dagtimer.c246 uint32_t cycles; in agtimer_rearm() local
250 cycles = (nsecs * sc->sc_nsec_cycle_ratio) >> 32; in agtimer_rearm()
251 if (cycles > INT32_MAX) in agtimer_rearm()
252 cycles = INT32_MAX; in agtimer_rearm()
253 agtimer_set_tval(cycles); in agtimer_rearm()
310 uint64_t cycles, start; in agtimer_delay() local
313 cycles = (uint64_t)usecs * agtimer_frequency / 1000000; in agtimer_delay()
314 while (agtimer_readcnt64() - start < cycles) in agtimer_delay()
/openbsd/sys/arch/sparc64/sparc64/
H A Dclock.c599 uint32_t cycles; in tick_rearm() local
603 cycles = (nsecs * tick_nsec_cycle_ratio) >> 32; in tick_rearm()
607 tickcmpr_set((t0 + cycles) & TICK_COUNT_MASK); in tick_rearm()
608 if (cycles <= ((tick() - t0) & TICK_COUNT_MASK)) in tick_rearm()
635 uint32_t cycles; in sys_tick_rearm() local
639 cycles = (nsecs * sys_tick_nsec_cycle_ratio) >> 32; in sys_tick_rearm()
643 sys_tickcmpr_set((t0 + cycles) & STICK_COUNT_MASK); in sys_tick_rearm()
668 uint32_t cycles; in stick_rearm() local
672 cycles = (nsecs * sys_tick_nsec_cycle_ratio) >> 32; in stick_rearm()
676 stickcmpr_set((t0 + cycles) & STICK_COUNT_MASK); in stick_rearm()
[all …]
/openbsd/sys/arch/amd64/amd64/
H A Dlapic.c426 uint32_t cycles; in lapic_timer_rearm() local
430 cycles = (nsecs * lapic_timer_nsec_cycle_ratio) >> 32; in lapic_timer_rearm()
431 if (cycles == 0) in lapic_timer_rearm()
432 cycles = 1; in lapic_timer_rearm()
433 lapic_writereg(LAPIC_ICR_TIMER, cycles); in lapic_timer_rearm()
454 lapic_timer_start(uint32_t mode, uint32_t mask, uint32_t cycles) in lapic_timer_start() argument
458 lapic_writereg(LAPIC_ICR_TIMER, cycles); in lapic_timer_start()
462 lapic_timer_oneshot(uint32_t mask, uint32_t cycles) in lapic_timer_oneshot() argument
464 lapic_timer_start(LAPIC_LVTT_TM_ONESHOT, mask, cycles); in lapic_timer_oneshot()
468 lapic_timer_periodic(uint32_t mask, uint32_t cycles) in lapic_timer_periodic() argument
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX3T110.td119 // 3 cycles on I1.
125 // 4 cycles on I1.
131 // 5 cycles on I1.
137 // 7 cycles on I1.
143 // 23 cycles on I1.
150 // 39 cycles on I1.
163 // 8 cycles on I2/I3
175 // 8 cycles on I1/I2/I3
241 // 4 cycles on F2/F3.
297 // 2 cycles on LS0/LS1.
[all …]
/openbsd/gnu/usr.bin/perl/dist/Thread-Queue/t/
H A D09_ended.t23 my $cycles = 2;
25 plan tests => 3*$num_threads*$cycles*$count + 6*$num_threads + 6;
29 my @items = 1..($num_threads*$cycles*$count);
51 for my $ii (1..($num_threads*$cycles)) {
72 my @items = 1..($num_threads*$cycles*$count + 1);
94 for my $ii (1..($num_threads*$cycles)) {
115 my @items = 1..($num_threads*$cycles*$count + 1);
/openbsd/sys/arch/macppc/macppc/
H A Dclock.c244 uint32_t cycles; in dec_rearm() local
248 cycles = (nsecs * dec_nsec_cycle_ratio) >> 32; in dec_rearm()
249 if (cycles > UINT32_MAX >> 1) in dec_rearm()
250 cycles = UINT32_MAX >> 1; in dec_rearm()
251 ppc_mtdec(cycles); in dec_rearm()
/openbsd/gnu/llvm/llvm/docs/
H A DCycleTerminology.rst30 4. In any depth-first search starting from the entry, the set of cycles
31 found in the CFG is the same. These are the *top-level cycles*
33 5. The *child cycles* (or simply cycles) nested inside a cycle C with
35 C is said to be the *parent* of these cycles.
37 Thus, cycles form an implementation-defined forest where each cycle C is
38 the parent of any child cycles nested inside C. The tree closely
70 - Non-header entry blocks of a cycle can be contained in child cycles.
112 natural loops. A possible hierarchy of cycles is::
152 hierarchy of cycles is::
190 hierarchy of cycles is::
[all …]
/openbsd/gnu/usr.bin/perl/
H A Dtime64.c397 const int cycles = (int)Perl_floor(m / (Time64_T) days_in_gregorian_cycle); in Perl_gmtime64_r() local
398 if( cycles ) { in Perl_gmtime64_r()
399 m -= (cycles * (Time64_T) days_in_gregorian_cycle); in Perl_gmtime64_r()
400 year += (cycles * years_in_gregorian_cycle); in Perl_gmtime64_r()
418 int cycles; in Perl_gmtime64_r() local
423 cycles = (int)Perl_ceil((m / (Time64_T) days_in_gregorian_cycle) + 1); in Perl_gmtime64_r()
424 if( cycles ) { in Perl_gmtime64_r()
425 m -= (cycles * (Time64_T) days_in_gregorian_cycle); in Perl_gmtime64_r()
426 year += (cycles * years_in_gregorian_cycle); in Perl_gmtime64_r()
/openbsd/sys/arch/hppa/dev/
H A Dclock.c161 uint32_t cycles, t0, t1; in itmr_rearm() local
166 cycles = (nsecs * itmr_nsec_cycle_ratio) >> 32; in itmr_rearm()
170 mtctl(t0 + cycles, CR_ITMR); in itmr_rearm()
178 if (cycles <= t1 - t0) { in itmr_rearm()
/openbsd/sys/arch/arm/cortex/
H A Dagtimer.c183 uint32_t cycles; in agtimer_rearm() local
187 cycles = (nsecs * sc->sc_nsec_cycle_ratio) >> 32; in agtimer_rearm()
188 if (cycles > INT32_MAX) in agtimer_rearm()
189 cycles = INT32_MAX; in agtimer_rearm()
190 agtimer_set_tval(cycles); in agtimer_rearm()
/openbsd/sys/arch/mips64/mips64/
H A Dclock.c172 uint32_t cycles, t0; in cp0_rearm_int5() local
177 cycles = (nsecs * cp0_nsec_cycle_ratio) >> 32; in cp0_rearm_int5()
186 cp0_set_compare(t0 + cycles); in cp0_rearm_int5()
187 if (cycles <= cp0_get_count() - t0) { in cp0_rearm_int5()

12345678910