Home
last modified time | relevance | path

Searched refs:dcfclk_deep_sleep_khz (Results 1 – 23 of 23) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c269 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in dcn2_update_clocks()
270 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn2_update_clocks()
272 …_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz)); in dcn2_update_clocks()
362 new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) { in dcn2_update_clocks_fpga()
363 clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn2_update_clocks_fpga()
482 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) in dcn2_are_clock_states_equal()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr.c254 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in rv1_update_clocks()
255 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in rv1_update_clocks()
269 …mu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_khz)); in rv1_update_clocks()
289 …mu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_khz)); in rv1_update_clocks()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/
H A Ddcn201_clk_mgr.c123 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) in dcn201_update_clocks()
124 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn201_update_clocks()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c239 …(should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep… in dcn3_update_clocks()
240 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn3_update_clocks()
241 …mu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz)); in dcn3_update_clocks()
444 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) in dcn3_are_clock_states_equal()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c207 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in dcn31_update_clocks()
208 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn31_update_clocks()
209 dcn31_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); in dcn31_update_clocks()
251 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz = in dcn31_update_clocks()
252 clk_mgr_base->clks.dcfclk_deep_sleep_khz; in dcn31_update_clocks()
318 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) in dcn31_are_clock_states_equal()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c196 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in dcn316_update_clocks()
197 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn316_update_clocks()
198 dcn316_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); in dcn316_update_clocks()
242 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz = in dcn316_update_clocks()
243 clk_mgr_base->clks.dcfclk_deep_sleep_khz; in dcn316_update_clocks()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c235 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in dcn314_update_clocks()
236 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn314_update_clocks()
237 dcn314_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); in dcn314_update_clocks()
279 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz = in dcn314_update_clocks()
280 clk_mgr_base->clks.dcfclk_deep_sleep_khz; in dcn314_update_clocks()
333 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) in dcn314_are_clock_states_equal()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c148 …new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) && !dc->debug.disable… in vg_update_clocks()
149 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in vg_update_clocks()
150 dcn301_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); in vg_update_clocks()
474 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) in vg_are_clock_states_equal()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c180 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in rn_update_clocks()
181 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in rn_update_clocks()
182 rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); in rn_update_clocks()
537 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) in rn_are_clock_states_equal()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_clk_mgr.c189 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in dcn315_update_clocks()
190 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn315_update_clocks()
191 dcn315_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); in dcn315_update_clocks()
238 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz = in dcn315_update_clocks()
239 clk_mgr_base->clks.dcfclk_deep_sleep_khz; in dcn315_update_clocks()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c519 …(should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep… in dcn32_update_clocks()
521 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn32_update_clocks()
522 …mu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz)); in dcn32_update_clocks()
893 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) in dcn32_are_clock_states_equal()
/openbsd/sys/dev/pci/drm/amd/display/dc/core/
H A Ddc_debug.c354 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
362 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
H A Damdgpu_dc.c4661 info->dcfClockDeepSleep = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz; in get_clock_requirements_for_state()
/openbsd/sys/dev/pci/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_trace.h499 __field(int, dcfclk_deep_sleep_khz)
517 __entry->dcfclk_deep_sleep_khz = clk->dcfclk_deep_sleep_khz;
542 __entry->dcfclk_deep_sleep_khz,
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer_debug.c477 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in dcn10_get_clock_states()
H A Ddcn10_hw_sequencer.c465 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in dcn10_log_hw_state()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c560 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 0; in dcn31_calculate_wm_and_dlg_fp()
/openbsd/sys/dev/pci/drm/amd/display/dc/
H A Ddc.h531 int dcfclk_deep_sleep_khz; member
/openbsd/sys/dev/pci/drm/amd/display/dmub/inc/
H A Ddmub_cmd.h1405 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ member
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn32/
H A Ddcn32_hwseq.c741 clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ; in dcn32_initialize_min_clocks()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c1365 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; in dcn32_calculate_dlg_params()
1473 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 0; in dcn32_calculate_dlg_params()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c1162 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000); in dcn_validate_bandwidth()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1155 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; in dcn20_calculate_dlg_params()