dcfclk_sta_targets (reference) in projects: openbsd

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Searched refs:dcfclk_sta_targets (Results 1 – 5 of 5) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn302/
H A D	dcn302_fpu.c	205 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn302_fpu_update_bw_bounding_box() local 242 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn302_fpu_update_bw_bounding_box() 244 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box() 246 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn302_fpu_update_bw_bounding_box() 249 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { in dcn302_fpu_update_bw_bounding_box() 250 dcfclk_sta_targets[i] = max_dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box() 271 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn302_fpu_update_bw_bounding_box() 283 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn302_fpu_update_bw_bounding_box() 284 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box() 297 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn303/
H A D	dcn303_fpu.c	201 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn303_fpu_update_bw_bounding_box() local 238 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn303_fpu_update_bw_bounding_box() 239 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box() 241 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn303_fpu_update_bw_bounding_box() 243 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { in dcn303_fpu_update_bw_bounding_box() 244 dcfclk_sta_targets[i] = max_dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box() 265 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn303_fpu_update_bw_bounding_box() 277 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn303_fpu_update_bw_bounding_box() 278 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box() 292 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn321/
H A D	dcn321_fpu.c	354 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; in build_synthetic_soc_states() local 435 entry.dcfclk_mhz = dcfclk_sta_targets[i]; in build_synthetic_soc_states() 703 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564}; in dcn321_update_bw_bounding_box_fpu() local 726 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn321_update_bw_bounding_box_fpu() 728 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; in dcn321_update_bw_bounding_box_fpu() 730 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn321_update_bw_bounding_box_fpu() 733 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { in dcn321_update_bw_bounding_box_fpu() 734 dcfclk_sta_targets[i] = max_dcfclk_mhz; in dcn321_update_bw_bounding_box_fpu() 756 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn321_update_bw_bounding_box_fpu() 769 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn321_update_bw_bounding_box_fpu() [all …]
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn30/
H A D	dcn30_resource.c	2102 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn30_update_bw_bounding_box() local 2134 if (dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn30_update_bw_bounding_box() 2136 dcfclk_sta_targets[num_dcfclk_sta_targets] = dcn30_bb_max_clk.max_dcfclk_mhz; in dcn30_update_bw_bounding_box() 2138 } else if (dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn30_update_bw_bounding_box() 2141 if (dcfclk_sta_targets[i] > dcn30_bb_max_clk.max_dcfclk_mhz) { in dcn30_update_bw_bounding_box() 2142 dcfclk_sta_targets[i] = dcn30_bb_max_clk.max_dcfclk_mhz; in dcn30_update_bw_bounding_box() 2166 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn30_update_bw_bounding_box() 2178 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { in dcn30_update_bw_bounding_box() 2179 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box() 2192 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn32/
H A D	dcn32_fpu.c	2540 entry.dcfclk_mhz = dcfclk_sta_targets[i]; in build_synthetic_soc_states() 2812 if (min_dcfclk > dcfclk_sta_targets[0]) in dcn32_update_bw_bounding_box_fpu() 2813 dcfclk_sta_targets[0] = min_dcfclk; in dcn32_update_bw_bounding_box_fpu() 2823 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn32_update_bw_bounding_box_fpu() 2825 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; in dcn32_update_bw_bounding_box_fpu() 2827 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { in dcn32_update_bw_bounding_box_fpu() 2830 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { in dcn32_update_bw_bounding_box_fpu() 2831 dcfclk_sta_targets[i] = max_dcfclk_mhz; in dcn32_update_bw_bounding_box_fpu() 2853 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { in dcn32_update_bw_bounding_box_fpu() 2866 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn32_update_bw_bounding_box_fpu() [all …]