Home
last modified time | relevance | path

Searched refs:dram_channel_width_bytes (Results 1 – 21 of 21) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.c176 dcn3_02_soc.dram_channel_width_bytes * in dcn302_get_optimal_dcfclk_fclk_for_uclk()
179 dcn3_02_soc.dram_channel_width_bytes * in dcn302_get_optimal_dcfclk_fclk_for_uclk()
214 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) in dcn302_fpu_update_bw_bounding_box()
215 dcn3_02_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; in dcn302_fpu_update_bw_bounding_box()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.c174 dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_dram_bw_use_normal_percent / 100); in dcn303_get_optimal_dcfclk_fclk_for_uclk()
176 dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100); in dcn303_get_optimal_dcfclk_fclk_for_uclk()
210 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) in dcn303_fpu_update_bw_bounding_box()
211 dcn3_03_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; in dcn303_fpu_update_bw_bounding_box()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c150 .dram_channel_width_bytes = 2,
169 …dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixe… in get_optimal_ntuple()
175 …dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixe… in get_optimal_ntuple()
178 …dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixe… in get_optimal_ntuple()
193 …dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixe… in calculate_net_bw_in_kbytes_sec()
584 dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_dram_bw_use_normal_percent / 100); in dcn321_get_optimal_dcfclk_fclk_for_uclk()
586 dcn3_21_soc.dram_channel_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100); in dcn321_get_optimal_dcfclk_fclk_for_uclk()
682 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) in dcn321_update_bw_bounding_box_fpu()
683 dcn3_21_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; in dcn321_update_bw_bounding_box_fpu()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn314/
H A Ddcn314_fpu.c156 .dram_channel_width_bytes = 4,
198 if (bw_params->dram_channel_width_bytes > 0) in dcn314_update_bw_bounding_box_fpu()
199 dcn3_14_soc.dram_channel_width_bytes = bw_params->dram_channel_width_bytes; in dcn314_update_bw_bounding_box_fpu()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c175 .dram_channel_width_bytes = 4,
271 .dram_channel_width_bytes = 4,
419 .dram_channel_width_bytes = 4,
672 if (bw_params->dram_channel_width_bytes > 0) in dcn315_update_bw_bounding_box()
673 dcn3_15_soc.dram_channel_width_bytes = bw_params->dram_channel_width_bytes; in dcn315_update_bw_bounding_box()
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu_socbb.h57 uint32_t dram_channel_width_bytes; member
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c597 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) in dcn30_fpu_update_dram_channel_width_bytes()
598 dcn3_0_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; in dcn30_fpu_update_dram_channel_width_bytes()
624 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_dram_bw_use_normal_percent / 100); in dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk()
626 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100); in dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk()
/openbsd/sys/dev/pci/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h230 unsigned int dram_channel_width_bytes; member
/openbsd/sys/dev/pci/drm/amd/display/include/
H A Dgrph_object_ctrl_defs.h188 unsigned int dram_channel_width_bytes; member
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c161 .dram_channel_width_bytes = 2,
443 dcn3_2_soc.dram_channel_width_bytes * in calculate_net_bw_in_kbytes_sec()
472 …dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_… in get_optimal_ntuple()
478 …dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_… in get_optimal_ntuple()
481 …dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_… in get_optimal_ntuple()
2288 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_dram_bw_use_normal_percent / 100); in dcn32_get_optimal_dcfclk_fclk_for_uclk()
2290 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100); in dcn32_get_optimal_dcfclk_fclk_for_uclk()
2771 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) in dcn32_update_bw_bounding_box_fpu()
2772 dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; in dcn32_update_bw_bounding_box_fpu()
H A Ddisplay_mode_vba_util_32.c3291 double IdealDRAMBandwidth = DRAMSpeed * soc->num_chans * soc->dram_channel_width_bytes; in dml32_get_return_bw_mbps()
3334 DRAMSpeed * soc->num_chans * soc->dram_channel_width_bytes in dml32_get_return_bw_mbps_vm_only()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/
H A Ddisplay_mode_structs.h219 double dram_channel_width_bytes; member
H A Ddisplay_mode_vba.c367 mode_lib->vba.DRAMChannelWidth = soc->dram_channel_width_bytes; // new! in fetch_socbb_params()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn301/
H A Ddcn301_fpu.c191 .dram_channel_width_bytes = 4,
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c544 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4; in dcn316_clk_mgr_helper_populate_bw_params()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c307 .dram_channel_width_bytes = 2,
418 .dram_channel_width_bytes = 2,
529 .dram_channel_width_bytes = 16,
743 .dram_channel_width_bytes = 4,
/openbsd/sys/dev/pci/drm/amd/display/dc/bios/
H A Dbios_parser2.c2353 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8; in get_vram_info_v23()
2372 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8; in get_vram_info_v24()
2391 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8; in get_vram_info_v25()
2410 info->dram_channel_width_bytes = (1 << info_v30->channel_width) / 8; in get_vram_info_v30()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c615 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4; in dcn31_clk_mgr_helper_populate_bw_params()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_clk_mgr.c569 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4; in dcn315_clk_mgr_helper_populate_bw_params()
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c688 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4; in dcn314_clk_mgr_helper_populate_bw_params()
/openbsd/sys/dev/pci/drm/amd/display/dc/dcn201/
H A Ddcn201_resource.c215 .dram_channel_width_bytes = 2,