| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_optc.c | 133 enum optc_dsc_mode dsc_mode, in optc2_set_dsc_config() argument
140 OPTC_DSC_MODE, dsc_mode); in optc2_set_dsc_config()
153 uint32_t *dsc_mode) in optc2_get_dsc_status() argument
158 OPTC_DSC_MODE, dsc_mode); in optc2_get_dsc_status()
500 OTG_CRC_DSC_MODE, params->dsc_mode, in optc2_configure_crc()
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| H A D | dcn20_optc.h | 97 enum optc_dsc_mode dsc_mode,
102 uint32_t *dsc_mode);
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| H A D | dcn20_stream_encoder.c | 281 enum optc_dsc_mode dsc_mode, in enc2_dp_set_dsc_config() argument
288 DP_DSC_MODE, dsc_mode, in enc2_dp_set_dsc_config()
356 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc2_read_state()
357 if (s->dsc_mode) { in enc2_read_state()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn314/ |
| H A D | dcn314_dio_stream_encoder.c | 384 enum optc_dsc_mode dsc_mode, in enc314_dp_set_dsc_config() argument
390 REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1); in enc314_dp_set_dsc_config()
401 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc314_read_state()
402 if (s->dsc_mode) { in enc314_read_state()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_dio_stream_encoder.c | 389 enum optc_dsc_mode dsc_mode, in enc32_dp_set_dsc_config() argument
395 REG_UPDATE(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode == OPTC_DSC_DISABLED ? 0 : 1); in enc32_dp_set_dsc_config()
406 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc32_read_state()
407 if (s->dsc_mode) { in enc32_read_state()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/inc/hw/ |
| H A D | timing_generator.h | 133 uint8_t dsc_mode; member
299 enum optc_dsc_mode dsc_mode,
303 uint32_t *dsc_mode);
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| H A D | stream_encoder.h | 122 uint32_t dsc_mode; // DISABLED 0; 1 or 2 indicate enabled state. member
244 enum optc_dsc_mode dsc_mode,
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_dio_stream_encoder.c | 307 enum optc_dsc_mode dsc_mode, in enc3_dp_set_dsc_config() argument
314 DP_DSC_MODE, dsc_mode, in enc3_dp_set_dsc_config()
395 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc3_read_state()
396 if (s->dsc_mode) { in enc3_read_state()
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| H A D | dcn30_optc.c | 185 enum optc_dsc_mode dsc_mode, in optc3_set_dsc_config() argument
191 optc2_set_dsc_config(optc, dsc_mode, dsc_bytes_per_pixel, dsc_slice_width); in optc3_set_dsc_config()
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| H A D | dcn30_optc.h | 346 enum optc_dsc_mode dsc_mode,
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| /openbsd/sys/dev/pci/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_hw_sequencer.c | 432 s.dsc_mode, in dcn10_log_hw_state()
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| /openbsd/sys/dev/pci/drm/amd/display/dc/core/ |
| H A D | amdgpu_dc.c | 621 param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0; in dc_stream_configure_crc()
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