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Searched refs:dummy_pstate_latency_us (Results 1 – 10 of 10) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c168 .dummy_pstate_latency_us = 5,
484 dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us; in dcn30_fpu_calculate_wm_and_dlg()
505 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn30_fpu_calculate_wm_and_dlg()
704 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn30_find_dummy_latency_index_for_fw_based_mclk_switch()
771 base->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38; in dcn3_fpu_build_wm_range_table()
773 base->bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9; in dcn3_fpu_build_wm_range_table()
775 base->bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8; in dcn3_fpu_build_wm_range_table()
777 base->bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5; in dcn3_fpu_build_wm_range_table()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c234 clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 50; in dcn32_build_wm_range_table_fpu()
236 clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9; in dcn32_build_wm_range_table_fpu()
238 clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8; in dcn32_build_wm_range_table_fpu()
240 clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5; in dcn32_build_wm_range_table_fpu()
279 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
2001 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn32_calculate_wm_and_dlg_fpu()
2160 dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us; in dcn32_calculate_wm_and_dlg_fpu()
2181 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn32_calculate_wm_and_dlg_fpu()
2266 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn32_calculate_wm_and_dlg_fpu()
2738 if ((int)(dcn3_2_soc.dummy_pstate_latency_us * 1000) in dcn32_update_bw_bounding_box_fpu()
[all …]
/openbsd/sys/dev/pci/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h224 double dummy_pstate_latency_us; member
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.c156 .dummy_pstate_latency_us = 5,
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/
H A Ddisplay_mode_structs.h236 double dummy_pstate_latency_us; member
H A Ddisplay_mode_vba.c359 mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us; in fetch_socbb_params()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.c155 .dummy_pstate_latency_us = 5,
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c296 .dummy_pstate_latency_us = 10.0
472 …ext->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us; in dcn315_update_soc_for_wm_a()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c649 if ((int)(dcn3_21_soc.dummy_pstate_latency_us * 1000) in dcn321_update_bw_bounding_box_fpu()
652 dcn3_21_soc.dummy_pstate_latency_us = in dcn321_update_bw_bounding_box_fpu()
/openbsd/sys/dev/pci/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c321 .dummy_pstate_latency_us = 5.0,
432 .dummy_pstate_latency_us = 5.0,
2012 if ((int)(bb->dummy_pstate_latency_us * 1000) in dcn20_patch_bounding_box()
2015 bb->dummy_pstate_latency_us = in dcn20_patch_bounding_box()
2100 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 || in dcn20_validate_bandwidth_fp()
2107 …ext->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us; in dcn20_validate_bandwidth_fp()