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Searched refs:dyn_state (Results 1 – 25 of 29) sorted by relevance

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/openbsd/sys/dev/pci/drm/amd/pm/legacy-dpm/
H A Dlegacy_dpm.c531 adev->pm.dpm.dyn_state.ppm_table = in amdgpu_parse_extended_power_table()
533 if (!adev->pm.dpm.dyn_state.ppm_table) in amdgpu_parse_extended_power_table()
546 adev->pm.dpm.dyn_state.ppm_table->apu_tdp = in amdgpu_parse_extended_power_table()
548 adev->pm.dpm.dyn_state.ppm_table->dgpu_tdp = in amdgpu_parse_extended_power_table()
552 adev->pm.dpm.dyn_state.ppm_table->tj_max = in amdgpu_parse_extended_power_table()
585 adev->pm.dpm.dyn_state.cac_tdp_table = in amdgpu_parse_extended_power_table()
587 if (!adev->pm.dpm.dyn_state.cac_tdp_table) in amdgpu_parse_extended_power_table()
634 struct amdgpu_dpm_dynamic_state *dyn_state = &adev->pm.dpm.dyn_state; in amdgpu_free_extended_power_table() local
640 kfree(dyn_state->cac_leakage_table.entries); in amdgpu_free_extended_power_table()
642 kfree(dyn_state->ppm_table); in amdgpu_free_extended_power_table()
[all …]
H A Damdgpu_si_dpm.c2632 &adev->pm.dpm.dyn_state.cac_leakage_table; in si_get_cac_std_voltage_max_min()
3299 adev->pm.dpm.dyn_state.mclk_sclk_ratio); in btc_adjust_clock_combinations()
3305 adev->pm.dpm.dyn_state.sclk_mclk_delta); in btc_adjust_clock_combinations()
4626 …adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4641 …adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
7492 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in si_dpm_init()
7493 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in si_dpm_init()
7494 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in si_dpm_init()
7495 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in si_dpm_init()
7505 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in si_dpm_init()
[all …]
H A Damdgpu_kv_dpm.c77 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
99 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
793 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
1154 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1770 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_set_valid_clock_range()
2166 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_get_high_voltage_limit()
2207 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_apply_state_adjust_rules()
2210 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_apply_state_adjust_rules()
2344 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_calculate_nbps_level_settings()
2411 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_init_graphics_levels()
[all …]
/openbsd/sys/dev/pci/drm/radeon/
H A Dr600_dpm.c1202 rdev->pm.dpm.dyn_state.ppm_table = in r600_parse_extended_power_table()
1204 if (!rdev->pm.dpm.dyn_state.ppm_table) { in r600_parse_extended_power_table()
1219 rdev->pm.dpm.dyn_state.ppm_table->apu_tdp = in r600_parse_extended_power_table()
1221 rdev->pm.dpm.dyn_state.ppm_table->dgpu_tdp = in r600_parse_extended_power_table()
1225 rdev->pm.dpm.dyn_state.ppm_table->tj_max = in r600_parse_extended_power_table()
1260 rdev->pm.dpm.dyn_state.cac_tdp_table = in r600_parse_extended_power_table()
1262 if (!rdev->pm.dpm.dyn_state.cac_tdp_table) { in r600_parse_extended_power_table()
1300 struct radeon_dpm_dynamic_state *dyn_state = &rdev->pm.dpm.dyn_state; in r600_free_extended_power_table() local
1306 kfree(dyn_state->cac_leakage_table.entries); in r600_free_extended_power_table()
1308 kfree(dyn_state->ppm_table); in r600_free_extended_power_table()
[all …]
H A Dbtc_dpm.c1284 rdev->pm.dpm.dyn_state.mclk_sclk_ratio); in btc_adjust_clock_combinations()
1290 rdev->pm.dpm.dyn_state.sclk_mclk_delta); in btc_adjust_clock_combinations()
2698 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in btc_dpm_init()
2699 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in btc_dpm_init()
2700 rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900; in btc_dpm_init()
2703 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in btc_dpm_init()
2704 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; in btc_dpm_init()
2707 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in btc_dpm_init()
2709 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 10000; in btc_dpm_init()
2714 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in btc_dpm_init()
[all …]
H A Dci_dpm.c395 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_vddc_base_leakage_sidd()
412 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_parameters_in_dpm_table()
647 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_enable_power_containment()
721 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_power_control_set_level()
1599 rdev->pm.dpm.dyn_state.cac_tdp_table;
3406 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_setup_default_dpm_tables()
3408 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_setup_default_dpm_tables()
3410 &rdev->pm.dpm.dyn_state.cac_leakage_table; in ci_setup_default_dpm_tables()
5778 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in ci_dpm_init()
5779 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in ci_dpm_init()
[all …]
H A Dsi_dpm.c2517 &rdev->pm.dpm.dyn_state.cac_leakage_table; in si_get_cac_std_voltage_max_min()
3956 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_construct_voltage_tables()
4149 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4164 …rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
7038 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in si_dpm_init()
7039 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in si_dpm_init()
7040 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in si_dpm_init()
7041 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in si_dpm_init()
7043 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in si_dpm_init()
7051 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in si_dpm_init()
[all …]
H A Dni_dpm.c1012 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in ni_patch_dependency_tables_based_on_leakage()
1015 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in ni_patch_dependency_tables_based_on_leakage()
1346 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries && in ni_get_std_voltage_value()
3101 &rdev->pm.dpm.dyn_state.cac_leakage_table; in ni_init_simplified_leakage_table()
4200 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 3; in ni_dpm_init()
4201 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in ni_dpm_init()
4202 rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900; in ni_dpm_init()
4205 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in ni_dpm_init()
4207 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 12500; in ni_dpm_init()
4266 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in ni_dpm_init()
[all …]
H A Dkv_dpm.c399 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
421 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
562 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
923 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1533 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_set_valid_clock_range()
1905 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_get_high_voltage_limit()
1946 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_apply_state_adjust_rules()
1949 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_apply_state_adjust_rules()
2083 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_calculate_nbps_level_settings()
2150 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_init_graphics_levels()
[all …]
H A Drv770_dpm.c2261 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in rv7xx_parse_pplib_clock_info()
2262 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in rv7xx_parse_pplib_clock_info()
2263 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in rv7xx_parse_pplib_clock_info()
2264 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; in rv7xx_parse_pplib_clock_info()
H A Dradeon_kms.c541 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; in radeon_info_ioctl()
/openbsd/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dprocesspptables.c1406 &hwmgr->dyn_state.cac_dtp_table, in init_clock_voltage_dependency()
1455 &hwmgr->dyn_state.valid_sclk_values, in init_clock_voltage_dependency()
1532 hwmgr->dyn_state.ppm_parameter_table = ptr; in get_platform_power_management_table()
1766 kfree(hwmgr->dyn_state.valid_mclk_values); in pp_tables_uninitialize()
1767 hwmgr->dyn_state.valid_mclk_values = NULL; in pp_tables_uninitialize()
1769 kfree(hwmgr->dyn_state.valid_sclk_values); in pp_tables_uninitialize()
1770 hwmgr->dyn_state.valid_sclk_values = NULL; in pp_tables_uninitialize()
1772 kfree(hwmgr->dyn_state.cac_leakage_table); in pp_tables_uninitialize()
1773 hwmgr->dyn_state.cac_leakage_table = NULL; in pp_tables_uninitialize()
1790 kfree(hwmgr->dyn_state.cac_dtp_table); in pp_tables_uninitialize()
[all …]
H A Dsmu8_hwmgr.c104 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_sclk_level()
262 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_construct_max_power_limits_table()
444 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_upload_pptable_to_smu()
446 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk; in smu8_upload_pptable_to_smu()
558 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_init_sclk_limit()
696 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_update_sclk_limit()
1031 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_populate_umdpstate_clocks()
1187 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_phm_unforce_dpm_levels()
1530 hwmgr->dyn_state.vddc_dep_on_dal_pwrl; in smu8_get_dal_power_level()
1532 &hwmgr->dyn_state.max_clock_voltage_on_ac; in smu8_get_dal_power_level()
[all …]
H A Dsmu7_hwmgr.c337 hwmgr->dyn_state.mvdd_dependency_on_mclk); in smu7_construct_voltage_tables()
357 hwmgr->dyn_state.vddci_dependency_on_mclk); in smu7_construct_voltage_tables()
382 hwmgr->dyn_state.vddc_dependency_on_mclk); in smu7_construct_voltage_tables()
785 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu7_setup_dpm_tables_v0()
787 hwmgr->dyn_state.vddc_dependency_on_mclk; in smu7_setup_dpm_tables_v0()
789 hwmgr->dyn_state.cac_leakage_table; in smu7_setup_dpm_tables_v0()
1522 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu7_populate_umdpstate_clocks()
2878 …if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk… in smu7_set_private_data_based_on_pptable_v0()
2879 …hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entrie… in smu7_set_private_data_based_on_pptable_v0()
2886 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); in smu7_hwmgr_backend_fini()
[all …]
H A Dhwmgr.c245 if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) || in hwmgr_hw_init()
246 (hwmgr->dyn_state.max_clock_voltage_on_dc.mclk == 0)) in hwmgr_hw_init()
247 hwmgr->dyn_state.max_clock_voltage_on_dc = in hwmgr_hw_init()
248 hwmgr->dyn_state.max_clock_voltage_on_ac; in hwmgr_hw_init()
H A Dprocess_pptables_v1_0.c582 hwmgr->dyn_state.cac_dtp_table = kzalloc(table_size, GFP_KERNEL); in get_cac_tdp_table()
584 if (NULL == hwmgr->dyn_state.cac_dtp_table) { in get_cac_tdp_table()
848 hwmgr->dyn_state.max_clock_voltage_on_dc.sclk = in init_clock_voltage_dependency()
850 hwmgr->dyn_state.max_clock_voltage_on_dc.mclk = in init_clock_voltage_dependency()
852 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = in init_clock_voltage_dependency()
854 hwmgr->dyn_state.max_clock_voltage_on_dc.vddci = in init_clock_voltage_dependency()
1219 kfree(hwmgr->dyn_state.cac_dtp_table); in pp_tables_v1_0_uninitialize()
1220 hwmgr->dyn_state.cac_dtp_table = NULL; in pp_tables_v1_0_uninitialize()
H A Dvega10_processpptables.c992 hwmgr->dyn_state.max_clock_voltage_on_dc.sclk = in init_powerplay_extended_tables()
994 hwmgr->dyn_state.max_clock_voltage_on_dc.mclk = in init_powerplay_extended_tables()
996 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = in init_powerplay_extended_tables()
998 hwmgr->dyn_state.max_clock_voltage_on_dc.vddci = in init_powerplay_extended_tables()
1231 kfree(hwmgr->dyn_state.cac_dtp_table); in vega10_pp_tables_uninitialize()
1232 hwmgr->dyn_state.cac_dtp_table = NULL; in vega10_pp_tables_uninitialize()
H A Dsmu10_hwmgr.c161 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; in smu10_init_dynamic_state_adjustment_rule_settings()
177 &hwmgr->dyn_state.max_clock_voltage_on_ac); in smu10_get_system_info_data()
615 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); in smu10_hwmgr_backend_fini()
616 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; in smu10_hwmgr_backend_fini()
H A Dppatomctrl.c1163 for (entry_id = 0; entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count; entry_id++) { in atomctrl_get_voltage_evv()
1164 if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].v == virtual_voltage_id) { in atomctrl_get_voltage_evv()
1170 if (entry_id >= hwmgr->dyn_state.vddc_dependency_on_sclk->count) { in atomctrl_get_voltage_evv()
1179 cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk); in atomctrl_get_voltage_evv()
H A Dvega10_hwmgr.c803 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = in vega10_set_private_data_based_on_pptable()
805 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = in vega10_set_private_data_based_on_pptable()
807 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = in vega10_set_private_data_based_on_pptable()
809 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = in vega10_set_private_data_based_on_pptable()
817 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); in vega10_hwmgr_backend_fini()
818 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; in vega10_hwmgr_backend_fini()
3310 &(hwmgr->dyn_state.max_clock_voltage_on_ac) : in vega10_apply_state_adjust_rules()
3311 &(hwmgr->dyn_state.max_clock_voltage_on_dc); in vega10_apply_state_adjust_rules()
3340 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); in vega10_apply_state_adjust_rules()
H A Dsmu7_powertune.c1160 cac_table = hwmgr->dyn_state.cac_dtp_table; in smu7_enable_power_containment()
1250 cac_table = hwmgr->dyn_state.cac_dtp_table; in smu7_power_control_set_level()
H A Dsmu_helper.c529 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; in phm_initializa_dynamic_state_adjustment_rule_settings()
/openbsd/sys/dev/pci/drm/amd/pm/powerplay/smumgr/
H A Dci_smumgr.c419 hwmgr->dyn_state.vddc_dependency_on_sclk, clock, in ci_populate_single_graphic_level()
431 hwmgr->dyn_state.vddc_phase_shed_limits_table, in ci_populate_single_graphic_level()
589 …PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_… in ci_populate_bapm_vddc_vid_sidd()
777 if (NULL == hwmgr->dyn_state.cac_leakage_table) { in ci_get_std_voltage_value_sidd()
790 …*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].V… in ci_get_std_voltage_value_sidd()
791 …*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->c… in ci_get_std_voltage_value_sidd()
806 …*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].V… in ci_get_std_voltage_value_sidd()
1196 hwmgr->dyn_state.vddci_dependency_on_mclk, in ci_populate_single_memory_level()
1205 hwmgr->dyn_state.mvdd_dependency_on_mclk, in ci_populate_single_memory_level()
2867 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc; in ci_update_uvd_smc_table()
[all …]
H A Diceland_smumgr.c396 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table, in iceland_populate_bapm_vddc_vid_sidd()
400 …PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_… in iceland_populate_bapm_vddc_vid_sidd()
544 if (NULL == hwmgr->dyn_state.cac_leakage_table) { in iceland_get_std_voltage_value_sidd()
562 …*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].V… in iceland_get_std_voltage_value_sidd()
563 …*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->c… in iceland_get_std_voltage_value_sidd()
582 …*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].V… in iceland_get_std_voltage_value_sidd()
583 …*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->c… in iceland_get_std_voltage_value_sidd()
902 hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock, in iceland_populate_single_graphic_level()
913 hwmgr->dyn_state.vddc_phase_shed_limits_table, in iceland_populate_single_graphic_level()
1240 if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) { in iceland_populate_single_memory_level()
[all …]
/openbsd/sys/dev/pci/drm/amd/pm/inc/
H A Damdgpu_dpm.h266 struct amdgpu_dpm_dynamic_state dyn_state; member

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