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/openbsd/sys/dev/pci/drm/i915/display/
H A Dintel_fifo_underrun.c122 if (enable) { in i9xx_set_fifo_underrun_reporting()
142 if (enable) in ilk_set_fifo_underrun_reporting()
171 if (enable) { in ivb_set_fifo_underrun_reporting()
210 if (enable) { in bdw_set_fifo_underrun_reporting()
229 if (enable) in ibx_set_fifo_underrun_reporting()
261 if (enable) { in cpt_set_fifo_underrun_reporting()
329 enable); in intel_set_cpu_fifo_underrun_reporting()
351 bool enable) in intel_set_pch_fifo_underrun_reporting() argument
375 enable); in intel_set_pch_fifo_underrun_reporting()
379 enable, old); in intel_set_pch_fifo_underrun_reporting()
[all …]
/openbsd/sys/dev/pci/drm/i915/
H A Di915_mitigations.c46 bool enable = true; in mitigations_set() local
64 enable = !enable; in mitigations_set()
69 enable = !enable; in mitigations_set()
78 if (enable) in mitigations_set()
104 bool enable; in mitigations_get() local
111 enable = false; in mitigations_get()
113 enable = true; in mitigations_get()
118 if ((local & BIT(i)) != enable) in mitigations_get()
122 "%s%s,", enable ? "" : "!", names[i]); in mitigations_get()
/openbsd/sys/dev/ic/
H A Ddwhdmiphy.c177 dwhdmi_phy_enable_power(struct dwhdmi_softc *sc, uint8_t enable) in dwhdmi_phy_enable_power() argument
183 reg |= (enable << HDMI_PHY_CONF0_PDZ_OFFSET); in dwhdmi_phy_enable_power()
188 dwhdmi_phy_enable_tmds(struct dwhdmi_softc *sc, uint8_t enable) in dwhdmi_phy_enable_tmds() argument
194 reg |= (enable << HDMI_PHY_CONF0_ENTMDS_OFFSET); in dwhdmi_phy_enable_tmds()
199 dwhdmi_phy_gen2_pddq(struct dwhdmi_softc *sc, uint8_t enable) in dwhdmi_phy_gen2_pddq() argument
205 reg |= (enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET); in dwhdmi_phy_gen2_pddq()
210 dwhdmi_phy_gen2_txpwron(struct dwhdmi_softc *sc, uint8_t enable) in dwhdmi_phy_gen2_txpwron() argument
216 reg |= (enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET); in dwhdmi_phy_gen2_txpwron()
227 reg |= (enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET); in dwhdmi_phy_sel_data_en_pol()
238 reg |= (enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET); in dwhdmi_phy_sel_interface_control()
[all …]
/openbsd/sys/dev/pci/drm/amd/display/dc/bios/
H A Dcommand_table.h51 bool enable);
57 bool enable,
62 bool enable,
67 bool enable);
70 bool enable);
77 bool enable);
81 bool enable);
H A Dcommand_table2.h51 bool enable);
57 bool enable,
62 bool enable,
67 bool enable);
70 bool enable);
77 bool enable);
81 bool enable);
/openbsd/sys/arch/octeon/dev/
H A Dcn30xxasx.c69 cn30xxasx_enable(struct cn30xxasx_softc *sc, int enable) in cn30xxasx_enable() argument
71 cn30xxasx_enable_tx(sc, enable); in cn30xxasx_enable()
72 cn30xxasx_enable_rx(sc, enable); in cn30xxasx_enable()
77 cn30xxasx_enable_tx(struct cn30xxasx_softc *sc, int enable) in cn30xxasx_enable_tx() argument
82 if (enable) in cn30xxasx_enable_tx()
91 cn30xxasx_enable_rx(struct cn30xxasx_softc *sc, int enable) in cn30xxasx_enable_rx() argument
96 if (enable) in cn30xxasx_enable_rx()
/openbsd/sys/dev/pci/drm/i915/gt/uc/
H A Dintel_guc_rc.c34 static int guc_action_control_gucrc(struct intel_guc *guc, bool enable) in guc_action_control_gucrc() argument
36 u32 rc_mode = enable ? INTEL_GUCRC_FIRMWARE_CONTROL : in guc_action_control_gucrc()
50 static int __guc_rc_control(struct intel_guc *guc, bool enable) in __guc_rc_control() argument
61 ret = guc_action_control_gucrc(guc, enable); in __guc_rc_control()
64 str_enable_disable(enable), ERR_PTR(ret)); in __guc_rc_control()
68 guc_info(guc, "RC %s\n", str_enabled_disabled(enable)); in __guc_rc_control()
/openbsd/sys/dev/pci/drm/amd/amdgpu/
H A Dnbio_v7_7.c52 if (enable) in nbio_v7_7_mc_access_enable()
109 bool enable) in nbio_v7_7_enable_doorbell_aperture() argument
115 BIF_DOORBELL_APER_EN, enable ? 1 : 0); in nbio_v7_7_enable_doorbell_aperture()
121 bool enable) in nbio_v7_7_enable_doorbell_selfring_aperture() argument
125 if (enable) { in nbio_v7_7_enable_doorbell_selfring_aperture()
253 bool enable) in nbio_v7_7_update_medium_grain_clock_gating() argument
261 if (enable) { in nbio_v7_7_update_medium_grain_clock_gating()
282 bool enable) in nbio_v7_7_update_medium_grain_light_sleep() argument
286 if (enable && !(adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) in nbio_v7_7_update_medium_grain_light_sleep()
290 if (enable) in nbio_v7_7_update_medium_grain_light_sleep()
[all …]
H A Dnbio_v7_0.c54 static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable) in nbio_v7_0_mc_access_enable() argument
56 if (enable) in nbio_v7_0_mc_access_enable()
106 bool enable) in nbio_v7_0_enable_doorbell_aperture() argument
108 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); in nbio_v7_0_enable_doorbell_aperture()
112 bool enable) in nbio_v7_0_enable_doorbell_selfring_aperture() argument
149 bool enable) in nbio_v7_0_update_medium_grain_clock_gating() argument
156 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) in nbio_v7_0_update_medium_grain_clock_gating()
167 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) in nbio_v7_0_update_medium_grain_clock_gating()
178 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) in nbio_v7_0_update_medium_grain_clock_gating()
188 bool enable) in nbio_v7_0_update_medium_grain_light_sleep() argument
[all …]
H A Dnbio_v7_2.c85 if (enable) in nbio_v7_2_mc_access_enable()
93 if (enable) in nbio_v7_2_mc_access_enable()
152 bool enable) in nbio_v7_2_enable_doorbell_aperture() argument
158 BIF_DOORBELL_APER_EN, enable ? 1 : 0); in nbio_v7_2_enable_doorbell_aperture()
164 bool enable) in nbio_v7_2_enable_doorbell_selfring_aperture() argument
168 if (enable) { in nbio_v7_2_enable_doorbell_selfring_aperture()
235 bool enable) in nbio_v7_2_update_medium_grain_clock_gating() argument
261 bool enable) in nbio_v7_2_update_medium_grain_light_sleep() argument
270 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) in nbio_v7_2_update_medium_grain_light_sleep()
280 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) in nbio_v7_2_update_medium_grain_light_sleep()
[all …]
H A Damdgpu_nbio.h68 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
76 bool enable);
78 bool enable);
82 bool enable);
84 bool enable);
86 bool enable);
93 bool enable);
H A Ddf_v1_7.c44 bool enable) in df_v1_7_enable_broadcast_mode() argument
48 if (enable) { in df_v1_7_enable_broadcast_mode()
78 bool enable) in df_v1_7_update_medium_grain_clock_gating() argument
85 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) { in df_v1_7_update_medium_grain_clock_gating()
113 bool enable) in df_v1_7_enable_ecc_force_par_wr_rmw() argument
116 ForceParWrRMW, enable); in df_v1_7_enable_ecc_force_par_wr_rmw()
H A Dhdp_v5_2.c44 bool enable) in hdp_v5_2_update_mem_power_gating() argument
84 if (enable) { in hdp_v5_2_update_mem_power_gating()
129 bool enable) in hdp_v5_2_update_medium_grain_clock_gating() argument
138 if (enable) { in hdp_v5_2_update_medium_grain_clock_gating()
185 bool enable) in hdp_v5_2_update_clock_gating() argument
187 hdp_v5_2_update_mem_power_gating(adev, enable); in hdp_v5_2_update_clock_gating()
188 hdp_v5_2_update_medium_grain_clock_gating(adev, enable); in hdp_v5_2_update_clock_gating()
H A Dhdp_v5_0.c52 bool enable) in hdp_v5_0_update_mem_power_gating() argument
94 if (enable) { in hdp_v5_0_update_mem_power_gating()
146 bool enable) in hdp_v5_0_update_medium_grain_clock_gating() argument
155 if (enable) { in hdp_v5_0_update_medium_grain_clock_gating()
177 bool enable) in hdp_v5_0_update_clock_gating() argument
179 hdp_v5_0_update_mem_power_gating(adev, enable); in hdp_v5_0_update_clock_gating()
180 hdp_v5_0_update_medium_grain_clock_gating(adev, enable); in hdp_v5_0_update_clock_gating()
H A Dathub_v2_0.c35 bool enable) in athub_v2_0_update_medium_grain_clock_gating() argument
44 if (enable) in athub_v2_0_update_medium_grain_clock_gating()
55 bool enable) in athub_v2_0_update_medium_grain_light_sleep() argument
65 if (enable) in athub_v2_0_update_medium_grain_light_sleep()
H A Dathub_v2_1.c34 bool enable) in athub_v2_1_update_medium_grain_clock_gating() argument
40 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) in athub_v2_1_update_medium_grain_clock_gating()
51 bool enable) in athub_v2_1_update_medium_grain_light_sleep() argument
57 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) && in athub_v2_1_update_medium_grain_light_sleep()
H A Dathub_v1_0.c33 bool enable) in athub_update_medium_grain_clock_gating() argument
39 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) in athub_update_medium_grain_clock_gating()
49 bool enable) in athub_update_medium_grain_light_sleep() argument
55 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) && in athub_update_medium_grain_light_sleep()
/openbsd/sys/dev/pci/drm/radeon/
H A Dtrinity_smc.c55 int trinity_dpm_bapm_enable(struct radeon_device *rdev, bool enable) in trinity_dpm_bapm_enable() argument
57 if (enable) in trinity_dpm_bapm_enable()
63 int trinity_dpm_config(struct radeon_device *rdev, bool enable) in trinity_dpm_config() argument
65 if (enable) in trinity_dpm_config()
98 bool enable) in trinity_dce_enable_voltage_adjustment() argument
100 if (enable) in trinity_dce_enable_voltage_adjustment()
H A Dr600_dpm.h143 void r600_gfx_clockgating_enable(struct radeon_device *rdev, bool enable);
144 void r600_dynamicpm_enable(struct radeon_device *rdev, bool enable);
145 void r600_enable_thermal_protection(struct radeon_device *rdev, bool enable);
147 void r600_enable_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable);
149 void r600_enable_sclk_control(struct radeon_device *rdev, bool enable);
150 void r600_enable_mclk_control(struct radeon_device *rdev, bool enable);
151 void r600_enable_spll_bypass(struct radeon_device *rdev, bool enable);
175 u32 index, bool enable);
177 u32 index, bool enable);
179 u32 index, bool enable);
[all …]
/openbsd/usr.sbin/ldpd/
H A Dsocket.c195 sock_set_reuse(int fd, int enable) in sock_set_reuse() argument
197 if (setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, &enable, in sock_set_reuse()
207 sock_set_bindany(int fd, int enable) in sock_set_bindany() argument
209 if (setsockopt(fd, SOL_SOCKET, SO_BINDANY, &enable, in sock_set_bindany()
230 sock_set_ipv4_recvif(int fd, int enable) in sock_set_ipv4_recvif() argument
232 if (setsockopt(fd, IPPROTO_IP, IP_RECVIF, &enable, in sock_set_ipv4_recvif()
233 sizeof(enable)) == -1) { in sock_set_ipv4_recvif()
319 sock_set_ipv6_pktinfo(int fd, int enable) in sock_set_ipv6_pktinfo() argument
321 if (setsockopt(fd, IPPROTO_IPV6, IPV6_RECVPKTINFO, &enable, in sock_set_ipv6_pktinfo()
322 sizeof(enable)) == -1) { in sock_set_ipv6_pktinfo()
H A Dinit.c241 err |= gen_cap_twcard_tlv(buf, enable); in send_capability()
244 err |= gen_cap_unotif_tlv(buf, enable); in send_capability()
271 int enable = 0; in recv_capability() local
318 enable = reserved & STATE_BIT; in recv_capability()
319 if (enable) in recv_capability()
326 (enable) ? "announced" : "withdrew"); in recv_capability()
343 enable = reserved & STATE_BIT; in recv_capability()
344 if (enable) in recv_capability()
414 gen_cap_twcard_tlv(struct ibuf *buf, int enable) in gen_cap_twcard_tlv() argument
421 if (enable) in gen_cap_twcard_tlv()
[all …]
/openbsd/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr_smu_msg.c93 void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable) in dcn32_smu_send_fclk_pstate_message() argument
95 smu_print("FCLK P-state support value is : %d\n", enable); in dcn32_smu_send_fclk_pstate_message()
98 DALSMC_MSG_SetFclkSwitchAllow, enable ? FCLK_PSTATE_SUPPORTED : FCLK_PSTATE_NOTSUPPORTED, NULL); in dcn32_smu_send_fclk_pstate_message()
143 void dcn32_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable) in dcn32_smu_wait_for_dmub_ack_mclk() argument
145 smu_print("PMFW to wait for DMCUB ack for MCLK : %d\n", enable); in dcn32_smu_wait_for_dmub_ack_mclk()
147 dcn32_smu_send_msg_with_param(clk_mgr, 0x14, enable ? 1 : 0, NULL); in dcn32_smu_wait_for_dmub_ack_mclk()
/openbsd/sys/dev/pci/drm/amd/display/dc/irq/
H A Dirq_service.c88 bool enable) in dal_irq_service_set_generic() argument
94 (info->enable_value[enable ? 0 : 1] & info->enable_mask); in dal_irq_service_set_generic()
101 bool enable) in dal_irq_service_set() argument
118 source, enable); in dal_irq_service_set()
122 return info->funcs->set(irq_service, info, enable); in dal_irq_service_set()
125 dal_irq_service_set_generic(irq_service, info, enable); in dal_irq_service_set()
/openbsd/sys/dev/pci/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_crtc.c73 int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable) in amdgpu_dm_crtc_set_vupdate_irq() argument
85 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY; in amdgpu_dm_crtc_set_vupdate_irq()
88 acrtc->crtc_id, enable ? "en" : "dis", rc); in amdgpu_dm_crtc_set_vupdate_irq()
106 if (vblank_work->enable) in vblank_control_worker()
126 if (vblank_work->enable) { in vblank_control_worker()
147 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable) in dm_set_vblank() argument
159 if (enable) { in dm_set_vblank()
171 rc = (enable) in dm_set_vblank()
190 work->enable = enable; in dm_set_vblank()
395 if (crtc_state->enable && in dm_crtc_helper_atomic_check()
/openbsd/gnu/gcc/fixincludes/
H A Dconfigure.ac9 # Figure out what compiler warnings we can enable.
17 # Only enable with --enable-werror-always until existing warnings are
43 [ --enable-twoprocess Use a separate process to apply the fixes],
95 AC_MSG_CHECKING([whether to enable maintainer-specific portions of Makefiles])
97 [ --enable-maintainer-mode enable make rules and dependencies not useful

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