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/openbsd/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFloat.td23 !strconcat("f64.", name), f64Inst>;
34 !strconcat("f64.", name), f64Inst>;
44 !strconcat("f64.", name), f64Inst>;
77 def : Pat<(frint f64:$src), (NEAREST_F64 f64:$src)>;
95 def : Pat<(seteq f64:$lhs, f64:$rhs), (EQ_F64 f64:$lhs, f64:$rhs)>;
96 def : Pat<(setne f64:$lhs, f64:$rhs), (NE_F64 f64:$lhs, f64:$rhs)>;
97 def : Pat<(setlt f64:$lhs, f64:$rhs), (LT_F64 f64:$lhs, f64:$rhs)>;
98 def : Pat<(setle f64:$lhs, f64:$rhs), (LE_F64 f64:$lhs, f64:$rhs)>;
99 def : Pat<(setgt f64:$lhs, f64:$rhs), (GT_F64 f64:$lhs, f64:$rhs)>;
100 def : Pat<(setge f64:$lhs, f64:$rhs), (GE_F64 f64:$lhs, f64:$rhs)>;
[all …]
H A DWebAssemblyInstrConv.td193 "f64.convert_i32_s\t$dst, $src", "f64.convert_i32_s",
197 "f64.convert_i32_u\t$dst, $src", "f64.convert_i32_u",
209 "f64.convert_i64_s\t$dst, $src", "f64.convert_i64_s",
213 "f64.convert_i64_u\t$dst, $src", "f64.convert_i64_u",
218 "f64.promote_f32\t$dst, $src", "f64.promote_f32",
239 "f64.reinterpret_i64\t$dst, $src",
240 "f64.reinterpret_i64", 0xbf>;
/openbsd/gnu/llvm/llvm/include/llvm/Analysis/
H A DVecFuncs.def72 TLI_DEFINE_VECFUNC("llvm.exp.f64", "_simd_exp_d2", FIXED(2))
88 TLI_DEFINE_VECFUNC("llvm.cos.f64", "_simd_cos_d2", FIXED(2))
93 TLI_DEFINE_VECFUNC("llvm.sin.f64", "_simd_sin_d2", FIXED(2))
103 TLI_DEFINE_VECFUNC("llvm.pow.f64", "_simd_pow_d2", FIXED(2))
209 TLI_DEFINE_VECFUNC("llvm.pow.f64", "__powd2", FIXED(2))
215 TLI_DEFINE_VECFUNC("llvm.exp.f64", "__expd2", FIXED(2))
219 TLI_DEFINE_VECFUNC("llvm.exp2.f64", "__exp2d2", FIXED(2))
225 TLI_DEFINE_VECFUNC("llvm.log.f64", "__logd2", FIXED(2))
235 TLI_DEFINE_VECFUNC("llvm.log2.f64", "__log2d2", FIXED(2))
241 TLI_DEFINE_VECFUNC("llvm.sin.f64", "__sind2", FIXED(2))
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCInstrVSX.td406 [(set f64:$XT, (any_fma f64:$XA, f64:$XB, f64:$XTi))]>,
422 [(set f64:$XT, (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi)))]>,
438 [(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, f64:$XTi)))]>,
454 [(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi))))]>,
2519 def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C),
2521 def : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)),
2523 def : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)),
2759 def : Pat<(f64 (fminnum_ieee f64:$A, f64:$B)),
2761 def : Pat<(f64 (fminnum_ieee (fcanonicalize f64:$A), f64:$B)),
2768 def : Pat<(f64 (fmaxnum_ieee f64:$A, f64:$B)),
[all …]
H A DPPCInstrSPE.td150 [(set f64:$RT, (any_fadd f64:$RA, f64:$RB))]>;
219 [(set f64:$RT, (any_fdiv f64:$RA, f64:$RB))]>;
223 [(set f64:$RT, (any_fmul f64:$RA, f64:$RB))]>;
235 [(set f64:$RT, (any_fsub f64:$RA, f64:$RB))]>;
859 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
861 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
863 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
867 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
869 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
873 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
[all …]
H A DREADME_P9.txt202 [(set f64:$XT, (PPCfrsqrte f64:$XB))]>;
314 (set i128:$XT, (int_ppc_vsx_xscmpeqdp f64:$XA, f64:$XB))
315 (set i128:$XT, (int_ppc_vsx_xscmpgedp f64:$XA, f64:$XB))
316 (set i128:$XT, (int_ppc_vsx_xscmpgtdp f64:$XA, f64:$XB))
317 (set i128:$XT, (int_ppc_vsx_xscmpnedp f64:$XA, f64:$XB))
467 (set f64:$XT, (fmaxnum f64:$XA, f64:$XB))
468 (set f64:$XT, (fminnum f64:$XA, f64:$XB))
471 (set f64:$XT, (int_ppc_vsx_xsmaxjdp f64:$XA, f64:$XB))
472 (set f64:$XT, (int_ppc_vsx_xsminjdp f64:$XA, f64:$XB))
515 . (set f64:$XT, (load iaddrX4:$src))
[all …]
H A DPPCInstrInfo.td2879 [(set f64:$FRT, (any_fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2907 [(set f64:$FRT, (fneg (any_fma f64:$FRA, f64:$FRC,
2924 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2934 [(set f64:$FRT, (any_fadd f64:$FRA, f64:$FRB))]>;
2943 [(set f64:$FRT, (any_fdiv f64:$FRA, f64:$FRB))]>;
2952 [(set f64:$FRT, (any_fmul f64:$FRA, f64:$FRC))]>;
3281 def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C),
3285 def : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)),
3289 def : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)),
3302 def : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (FMSUB $A, $B, $C)>;
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/ARM/
H A DARMCallingConv.td32 // Handle all vector types as either f64 or v2f64.
43 CCIfType<[f64], CCAssignToStack<8, 4>>,
58 // Handle all vector types as either f64 or v2f64.
73 // Handle all vector types as either f64 or v2f64.
93 // Handle all vector types as either f64 or v2f64.
110 // Handle all vector types as either f64 or v2f64.
115 CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,
133 // i64/f64 is passed in even pairs of GPRs
167 // Handle all vector types as either f64 or v2f64.
185 // Handle all vector types as either f64 or v2f64.
[all …]
H A DARMInstrVFP.td99 def vfp_f64imm : Operand<f64>,
100 PatLeaf<(f64 fpimm), [{
542 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>,
571 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>,
838 def : FP16Pat<(f64 (f16_to_fp GPR:$a)),
863 def : FP16Pat<(fp_to_f16 (f64 DPR:$a)),
1042 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
1054 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"),
1084 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
1096 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"),
[all …]
H A DARMInstrCDE.td552 def : Pat<(f64 (int_arm_cde_vcx1 timm:$coproc, timm:$imm)),
553 (f64 (CDE_VCX1_fpdp p_imm:$coproc, imm_11b:$imm))>;
554 def : Pat<(f64 (int_arm_cde_vcx1a timm:$coproc, (f64 DPR:$acc), timm:$imm)),
555 (f64 (CDE_VCX1A_fpdp p_imm:$coproc, DPR:$acc, imm_11b:$imm))>;
562 def : Pat<(f64 (int_arm_cde_vcx2 timm:$coproc, (f64 DPR:$n), timm:$imm)),
563 (f64 (CDE_VCX2_fpdp p_imm:$coproc, DPR:$n, imm_6b:$imm))>;
564 def : Pat<(f64 (int_arm_cde_vcx2a timm:$coproc, (f64 DPR:$acc), (f64 DPR:$n),
576 def : Pat<(f64 (int_arm_cde_vcx3 timm:$coproc, (f64 DPR:$n), (f64 DPR:$m),
579 def : Pat<(f64 (int_arm_cde_vcx3a timm:$coproc, (f64 DPR:$acc), (f64 DPR:$n),
580 (f64 DPR:$m), timm:$imm)),
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsCallingConv.td57 CCBitConvertToType<f64>,
90 CCIfType<[f64], CCAssignToStack<8, 8>>
157 // f64 arguments are passed in double precision FP registers.
165 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
185 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
216 // f64 are returned in registers D0, D2
217 CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>>
225 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()",
241 CCIfType<[f64], CCAssignToStack<8, 8>>
258 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
[all …]
/openbsd/sys/arch/sparc64/sparc64/
H A Ddb_trace.c101 struct frame *f64; in db_stack_trace_print() local
107 f64 = (struct frame *)(frame + BIAS); in db_stack_trace_print()
108 pc = (vaddr_t)KLOAD(f64->fr_pc); in db_stack_trace_print()
110 frame = KLOAD(f64->fr_fp); in db_stack_trace_print()
138 f64 = (struct frame *)(frame + BIAS); in db_stack_trace_print()
140 (*pr)("%lx, ", (long)KLOAD(f64->fr_arg[i])); in db_stack_trace_print()
141 (*pr)("%lx) at ", (long)KLOAD(f64->fr_arg[i])); in db_stack_trace_print()
150 struct frame *f64; in stacktrace_save_at() local
162 f64 = (struct frame *)(frame + BIAS); in stacktrace_save_at()
163 pc = (vaddr_t)KLOAD(f64->fr_pc); in stacktrace_save_at()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYCallingConv.td49 CCIfType<[f64], CCCustom<"CC_CSKY_ABIV2_SOFT_64">>,
50 CCIfType<[f64], CCAssignToStack<8, 4>>
59 CCIfType<[f64], CCCustom<"Ret_CSKY_ABIV2_SOFT_64">>
71 CCIfType<[f64], CCAssignToReg<[F0_64, F1_64, F2_64, F3_64]>>,
72 CCIfType<[f64], CCAssignToStack<8, 4>>
81 CCIfType<[f64], CCAssignToReg<[F0_64]>>
/openbsd/sys/arch/mips64/mips64/
H A Dfp_emulate.c864 f64 &= ~(1L << 63); in fpu_abs()
865 raw = (uint64_t)f64; in fpu_abs()
889 rslt = (uint64_t)f64; in fpu_add()
1121 rslt = (uint64_t)f64; in fpu_div()
1326 f64 ^= 1L << 63; in fpu_neg()
1363 f64 ^= 1L << 63; in fpu_nmadd()
1399 f64 ^= 1L << 63; in fpu_nmsub()
1424 raw = (uint64_t)f64; in fpu_recip()
1469 f64 = float64_div(ONE_F64, f64); in fpu_rsqrt()
1470 raw = (uint64_t)f64; in fpu_rsqrt()
[all …]
/openbsd/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchFloat64InstrInfo.td233 defm : LdPat<load, FLD_D, f64>;
234 def : RegRegLdPat<load, FLDX_D, f64>;
238 defm : StPat<store, FST_D, FPR64, f64>;
239 def : RegRegStPat<store, FSTX_D, FPR64, f64>;
247 // f64 -> f32
249 // f32 -> f64
250 def : Pat<(f64 (fpextend FPR32:$src)), (FCVT_D_S FPR32:$src)>;
278 def : Pat<(f64 fpimm0), (MOVGR2FR_D R0)>;
279 def : Pat<(f64 fpimm0neg), (FNEG_D (MOVGR2FR_D R0))>;
283 def : Pat<(f64 fpimm0), (MOVGR2FRH_W (MOVGR2FR_W_64 R0), R0)>;
[all …]
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/
H A DValueTypes.td34 def f64 : ValueType<64, 13>; // 64-bit floating point value
158 def v1f64 : ValueType<64, 125>; // 1 x f64 vector value
159 def v2f64 : ValueType<128, 126>; // 2 x f64 vector value
160 def v3f64 : ValueType<192, 127>; // 3 x f64 vector value
161 def v4f64 : ValueType<256, 128>; // 4 x f64 vector value
162 def v8f64 : ValueType<512, 129>; // 8 x f64 vector value
163 def v16f64 : ValueType<1024, 130>; // 16 x f64 vector value
164 def v32f64 : ValueType<2048, 131>; // 32 x f64 vector value
165 def v64f64 : ValueType<4096, 132>; // 64 x f64 vector value
166 def v128f64 : ValueType<8192, 133>; // 128 x f64 vector value
[all …]
/openbsd/gnu/llvm/compiler-rt/lib/builtins/arm/
H A Dextendsfdf2vfp.S22 vcvt.f64.f32 d0, s0
25 vcvt.f64.f32 d7, s15 // convert single to double
H A Dtruncdfsf2vfp.S22 vcvt.f32.f64 s0, d0
25 vcvt.f32.f64 s15, d7 // convert double to single (trucate precision)
H A Dfixdfsivfp.S22 vcvt.s32.f64 s0, d0
26 vcvt.s32.f64 s15, d7 // convert double to 32-bit int into s15
H A Dfixunsdfsivfp.S23 vcvt.u32.f64 s0, d0
27 vcvt.u32.f64 s15, d7 // convert double to 32-bit int into s15
H A Dfloatsidfvfp.S23 vcvt.f64.s32 d0, s0
26 vcvt.f64.s32 d7, s15 // convert 32-bit int in s15 to double in d7
H A Dfloatunssidfvfp.S23 vcvt.f64.u32 d0, s0
26 vcvt.f64.u32 d7, s15 // convert 32-bit int in s15 to double in d7
H A Ddivdf3vfp.S21 vdiv.f64 d0, d0, d1
25 vdiv.f64 d5, d6, d7
H A Dmuldf3vfp.S21 vmul.f64 d0, d0, d1
25 vmul.f64 d6, d6, d7
H A Dadddf3vfp.S20 vadd.f64 d0, d0, d1
24 vadd.f64 d6, d6, d7

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