/openbsd/sys/dev/pci/drm/amd/pm/swsmu/ |
H A D | smu_cmn.c | 589 uint64_t *feature_mask) in smu_cmn_get_enabled_mask() argument 595 if (!feature_mask) in smu_cmn_get_enabled_mask() 645 uint64_t feature_mask, in smu_cmn_feature_update_enable_state() argument 653 lower_32_bits(feature_mask), in smu_cmn_feature_update_enable_state() 659 upper_32_bits(feature_mask), in smu_cmn_feature_update_enable_state() 664 lower_32_bits(feature_mask), in smu_cmn_feature_update_enable_state() 670 upper_32_bits(feature_mask), in smu_cmn_feature_update_enable_state() 712 uint64_t feature_mask; in smu_cmn_get_pp_feature_mask() local 721 upper_32_bits(feature_mask), lower_32_bits(feature_mask)); in smu_cmn_get_pp_feature_mask() 757 uint64_t feature_mask; in smu_cmn_set_pp_feature_mask() local [all …]
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H A D | smu_cmn.h | 75 uint64_t *feature_mask); 82 uint64_t feature_mask,
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H A D | smu_internal.h | 75 …e smu_get_allowed_feature_mask(smu, feature_mask, num) smu_ppt_funcs(get_allowed_feature_mask, 0,… argument
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/openbsd/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ |
H A D | hwmgr.c | 102 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init() 113 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init() 118 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init() 123 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init() 131 hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK; in hwmgr_early_init() 144 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); in hwmgr_early_init() 149 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); in hwmgr_early_init() 160 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init() 170 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init() 443 if (hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK) in hwmgr_set_user_specify_caps() [all …]
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H A D | vega20_hwmgr.c | 103 if (!(hwmgr->feature_mask & PP_PCIE_DPM_MASK)) in vega20_set_default_registry_data() 106 if (!(hwmgr->feature_mask & PP_SCLK_DPM_MASK)) in vega20_set_default_registry_data() 109 if (!(hwmgr->feature_mask & PP_SOCCLK_DPM_MASK)) in vega20_set_default_registry_data() 112 if (!(hwmgr->feature_mask & PP_MCLK_DPM_MASK)) in vega20_set_default_registry_data() 118 if (!(hwmgr->feature_mask & PP_ULV_MASK)) in vega20_set_default_registry_data() 1828 (feature_mask & FEATURE_DPM_UCLK_MASK)) { in vega20_upload_dpm_min_level() 1839 (feature_mask & FEATURE_DPM_UVD_MASK)) { in vega20_upload_dpm_min_level() 1860 (feature_mask & FEATURE_DPM_VCE_MASK)) { in vega20_upload_dpm_min_level() 1884 (feature_mask & FEATURE_DPM_FCLK_MASK)) { in vega20_upload_dpm_min_level() 1942 (feature_mask & FEATURE_DPM_UVD_MASK)) { in vega20_upload_dpm_max_level() [all …]
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H A D | vega10_hwmgr.c | 141 hwmgr->feature_mask & PP_ULV_MASK ? true : false; in vega10_set_default_registry_data() 153 hwmgr->feature_mask & PP_AVFS_MASK ? true : false; in vega10_set_default_registry_data() 2892 uint32_t i, feature_mask = 0; in vega10_stop_dpm() local 2908 feature_mask |= data->smu_features[i]. in vega10_stop_dpm() 2931 uint32_t i, feature_mask = 0; in vega10_start_dpm() local 2937 feature_mask |= data->smu_features[i]. in vega10_start_dpm() 2946 true, feature_mask)) { in vega10_start_dpm() 2949 feature_mask) in vega10_start_dpm() 5648 uint32_t feature_mask = 0; in vega10_disable_power_features_for_compute_performance() local 5674 if (feature_mask) in vega10_disable_power_features_for_compute_performance() [all …]
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H A D | smu7_clockpowergating.c | 175 if (!(hwmgr->feature_mask & PP_ENABLE_GFX_CG_THRU_SMU)) in smu7_update_clock_gatings()
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/openbsd/sys/dev/pci/drm/amd/pm/swsmu/smu13/ |
H A D | smu_v13_0_7_ppt.c | 258 uint32_t *feature_mask, uint32_t num) in smu_v13_0_7_get_allowed_feature_mask() argument 265 memset(feature_mask, 0, sizeof(uint32_t) * num); in smu_v13_0_7_get_allowed_feature_mask() 276 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); in smu_v13_0_7_get_allowed_feature_mask() 296 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); in smu_v13_0_7_get_allowed_feature_mask() 298 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT); in smu_v13_0_7_get_allowed_feature_mask() 299 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT); in smu_v13_0_7_get_allowed_feature_mask() 300 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT); in smu_v13_0_7_get_allowed_feature_mask() 303 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT); in smu_v13_0_7_get_allowed_feature_mask() 304 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT); in smu_v13_0_7_get_allowed_feature_mask() 313 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT); in smu_v13_0_7_get_allowed_feature_mask() [all …]
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H A D | smu_v13_0_0_ppt.c | 289 uint32_t *feature_mask, uint32_t num) in smu_v13_0_0_get_allowed_feature_mask() argument 297 memset(feature_mask, 0xff, sizeof(uint32_t) * num); in smu_v13_0_0_get_allowed_feature_mask() 300 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); in smu_v13_0_0_get_allowed_feature_mask() 301 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT); in smu_v13_0_0_get_allowed_feature_mask() 309 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); in smu_v13_0_0_get_allowed_feature_mask() 315 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT); in smu_v13_0_0_get_allowed_feature_mask() 318 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT); in smu_v13_0_0_get_allowed_feature_mask() 324 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); in smu_v13_0_0_get_allowed_feature_mask() 327 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT); in smu_v13_0_0_get_allowed_feature_mask() 328 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT); in smu_v13_0_0_get_allowed_feature_mask() [all …]
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H A D | smu_v13_0_6_ppt.c | 287 uint32_t *feature_mask, in smu_v13_0_6_get_allowed_feature_mask() argument 294 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); in smu_v13_0_6_get_allowed_feature_mask() 1007 uint32_t feature_mask, uint32_t level) in smu_v13_0_6_upload_dpm_level() argument 1014 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK))) { in smu_v13_0_6_upload_dpm_level() 1030 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK))) { in smu_v13_0_6_upload_dpm_level() 1047 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK))) { in smu_v13_0_6_upload_dpm_level() 1645 uint64_t *feature_mask) in smu_v13_0_6_get_enabled_mask() argument 1651 ret = smu_cmn_get_enabled_mask(smu, feature_mask); in smu_v13_0_6_get_enabled_mask() 1654 *feature_mask = 0; in smu_v13_0_6_get_enabled_mask()
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H A D | aldebaran_ppt.c | 298 uint32_t *feature_mask, uint32_t num) in aldebaran_get_allowed_feature_mask() argument 304 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); in aldebaran_get_allowed_feature_mask() 938 uint32_t feature_mask, in aldebaran_upload_dpm_level() argument 947 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) { in aldebaran_upload_dpm_level() 961 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) { in aldebaran_upload_dpm_level() 975 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) { in aldebaran_upload_dpm_level() 1670 uint32_t feature_mask; member 1696 if (throttler_status & logging_label[throttler_idx].feature_mask) { in aldebaran_log_thermal_throttling_event()
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H A D | smu_v13_0.c | 781 uint32_t feature_mask[2]; in smu_v13_0_set_allowed_mask() local 787 bitmap_to_arr32(feature_mask, feature->allowed, 64); in smu_v13_0_set_allowed_mask() 790 feature_mask[1], NULL); in smu_v13_0_set_allowed_mask() 796 feature_mask[0], in smu_v13_0_set_allowed_mask()
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/openbsd/sys/dev/pci/drm/amd/pm/powerplay/smumgr/ |
H A D | vega10_smumgr.h | 46 bool enable, uint32_t feature_mask);
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H A D | vega12_smumgr.h | 52 bool enable, uint64_t feature_mask);
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H A D | vega20_smumgr.h | 51 bool enable, uint64_t feature_mask);
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H A D | vega12_smumgr.c | 126 bool enable, uint64_t feature_mask) in vega12_enable_smc_features() argument 130 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT); in vega12_enable_smc_features() 131 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT); in vega12_enable_smc_features()
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H A D | vega20_smumgr.c | 318 bool enable, uint64_t feature_mask) in vega20_enable_smc_features() argument 323 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT); in vega20_enable_smc_features() 324 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT); in vega20_enable_smc_features()
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H A D | vega10_smumgr.c | 112 bool enable, uint32_t feature_mask) in vega10_enable_smc_features() argument 126 msg, feature_mask, NULL); in vega10_enable_smc_features()
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/openbsd/sys/dev/pci/drm/amd/pm/swsmu/smu11/ |
H A D | cyan_skillfish_ppt.c | 566 uint64_t *feature_mask) in cyan_skillfish_get_enabled_mask() argument 568 if (!feature_mask) in cyan_skillfish_get_enabled_mask() 570 memset(feature_mask, 0xff, sizeof(*feature_mask)); in cyan_skillfish_get_enabled_mask()
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H A D | navi10_ppt.c | 279 uint32_t *feature_mask, uint32_t num) in navi10_get_allowed_feature_mask() argument 286 memset(feature_mask, 0, sizeof(uint32_t) * num); in navi10_get_allowed_feature_mask() 314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); in navi10_get_allowed_feature_mask() 320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); in navi10_get_allowed_feature_mask() 326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); in navi10_get_allowed_feature_mask() 329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); in navi10_get_allowed_feature_mask() 335 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT); in navi10_get_allowed_feature_mask() 338 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT); in navi10_get_allowed_feature_mask() 341 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); in navi10_get_allowed_feature_mask() 351 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) in navi10_get_allowed_feature_mask() [all …]
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H A D | sienna_cichlid_ppt.c | 276 uint32_t *feature_mask, uint32_t num) in sienna_cichlid_get_allowed_feature_mask() argument 283 memset(feature_mask, 0, sizeof(uint32_t) * num); in sienna_cichlid_get_allowed_feature_mask() 314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT); in sienna_cichlid_get_allowed_feature_mask() 317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) in sienna_cichlid_get_allowed_feature_mask() 322 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); in sienna_cichlid_get_allowed_feature_mask() 331 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); in sienna_cichlid_get_allowed_feature_mask() 334 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); in sienna_cichlid_get_allowed_feature_mask() 337 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); in sienna_cichlid_get_allowed_feature_mask() 340 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); in sienna_cichlid_get_allowed_feature_mask() 343 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); in sienna_cichlid_get_allowed_feature_mask() [all …]
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H A D | arcturus_ppt.c | 316 uint32_t *feature_mask, uint32_t num) in arcturus_get_allowed_feature_mask() argument 322 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); in arcturus_get_allowed_feature_mask() 949 uint32_t feature_mask, in arcturus_upload_dpm_level() argument 958 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) { in arcturus_upload_dpm_level() 972 (feature_mask & FEATURE_DPM_UCLK_MASK)) { in arcturus_upload_dpm_level() 986 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) { in arcturus_upload_dpm_level() 2304 uint32_t feature_mask; member 2332 if (throttler_status & logging_label[throttler_idx].feature_mask) { in arcturus_log_thermal_throttling_event()
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H A D | smu_v11_0.c | 751 uint32_t feature_mask[2]; in smu_v11_0_set_allowed_mask() local 758 bitmap_to_arr32(feature_mask, feature->allowed, 64); in smu_v11_0_set_allowed_mask() 761 feature_mask[1], NULL); in smu_v11_0_set_allowed_mask() 766 feature_mask[0], NULL); in smu_v11_0_set_allowed_mask()
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/openbsd/sys/dev/pci/drm/amd/pm/swsmu/smu12/ |
H A D | renoir_ppt.c | 1414 uint64_t *feature_mask) in renoir_get_enabled_mask() argument 1416 if (!feature_mask) in renoir_get_enabled_mask() 1418 memset(feature_mask, 0xff, sizeof(*feature_mask)); in renoir_get_enabled_mask()
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/openbsd/sys/dev/pci/drm/amd/pm/swsmu/inc/ |
H A D | amdgpu_smu.h | 586 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 1017 int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask);
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